Lecture 18 Physical Design and Layout of Diodes and Transistors

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Lecture 18Physical Design and Layout of Diodes
and Transistors

• Diode physical design
• Bipolar and MOSFET transistor physical design
• Summary

• Michael L. Bushnell
• CAIP Center and WINLAB
• ECE Dept., Rutgers U., Piscataway, NJ

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Diode Properties

• Applies to abrupt pn junction
• For a graded junction
• Junction breakdown (abrupt junction)
• Occurs at metallurgical junction
• Neglect Y0

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Process Extensions for Better Cs, Diodes,
Transistors

• Silicide reduces r of poly
• Can use on source drain diffusion to reduce
  parasitic R in submicron processes
• In older processes, silicided contacts prevent
  contact spiking
• Schottky diode
• Anode is silicided contact
• Cathode is n-well (contacted through n substrate
  diffusion)
• No buried layer increases internal R of diode,
  making it unsuitable for high currents

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MOSFET Transistor

• Small signal model
• Design them to operate in saturation in analog
  circuits
• Less noise
• More linear behavior

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Early Voltage

• Depletion region exists between end of channel
  (at pinch-off) and the drain
• Effective channel length Leff L Xd
• In saturation, define a voltage similar to VA
  (Early voltage)
• Use l (channel length modulation parameter) to
  characterize l 1 / VA

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Bipolar Transistor Output Characteristics Showing
Early Voltage VA
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Updated Saturation Equation

• Problem Field distribution in drain depletion
  area is multi-dimensional
• Calculate l from experimental data.
• NMOS device
• characteristics

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Large-Signal Model for nMOS

• When L lt 10 mm, drain depletion region influences
  channel
• Make L long in analog devices then it follows
  the ideal case
• Gate oxide breaks down when VGS gt 50 V

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Small Signal Saturated MOSFET Model

• Body effect Source substrate voltage VBS affects
  Vt, and thus ID
• Need ID to be a function of both VGS and VBS
• Need two transconductance generators in model

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Gate Transconductance

• When l VDS ltlt 1
• 
  
  - c is the
  rate of change of threshold with body bias
• (C / unit area of depletion area under channel)

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MOSFET Transconductance Ratio

• Important!
• Ranges from 0.1 to 0.3

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Small Signal Output Resistance

• Channel length modulation

?ID
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Small Signal Parasitic C

• Cgs is intrinsic to device operation in
  saturation
• Treat Cgb as constant, lt 0.1 pF
• Cgs Cgd Total C under gate is Cox W L
• Ohmic region Splits equally between source and
  drain
• Cgs Cgd ½ Cox W L

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Cgs in Saturation

• Saturation region -- Channel very narrow at drain
• Cgd 0, except for a constant parasitic gate
  overlap capacitance 1 to 10 fF
• To get this, calculate stored channel charge
• y L is the point where V (VGS Vt)
• Also get a parasitic overlap C from the source
  region

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Example
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Example (continued)
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Threshold Voltages

• 3 V polysilicon CMOS - Digital VT 0.6
  0.15 V
• Analog CMOS may have reduced threshold compared
  with digital CMOS

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Analog Transistor Fabrication

• p type (100) crystal substrate heavy Boron (B)
  doping to minimize substrate resistivity
• Avoids latchup by minimizing substrate biasing
• Epitaxial growth grow lightly doped p-epi on
  substrate

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Epitaxial Layer

• 5 to 10 mm thick
• Benefits
• Improves latchup immunity through p substrate
• Electrical properties of epitaxial layer are
  better controlled than those of Czochralski
  process

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Analog Transistor Fabrication Process

• Thermal oxidation, photoresist, n-well mask
• Create n-well using phosphorous (P) nMOS in epi,
  pMOS in n-well
• Total dopant concentration due to counter-doping
  in well degrades
• mn in n-well region optimize nMOSFET at expense
  of pMOSFET
• Allows a grounded substrate

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Transistor Fabrication Process

• Inverse Moat
• Use thick field oxide to reduce C between metal
  silicon
• Use local oxidation of silicon (LOCOS) to grow
  field oxide
• Leaves only thin pad oxide (thinox) over
  transistor regions
• Field regions field oxide
• Moat region protected from oxidation

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Moat Growth

• Use patterned SiN layer to create moats with
  inverse moat mask
• Must be placed on top of thin SiO2 layer
• Nitride growth mechanically stresses Si crystal
• Can cause Si lattice dislocations

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Channel Stop Implants

• Needed to ensure that thick field thresholds
  exceed operating voltages
• Put dopant beneath thick field oxide to raise
  thresholds of thick field transistors
• Ion implant
• p-epi field gets p-type implant
• n-well field gets n-type implant
• Expose all channel stops to Boron
• Expose only n-well channel stops to Phosphorous
  (counterdoping)

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Wafer After Blanket Boron Channel Stop Implant

• (B) After selective phosphorous channel stop
  implant

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LOCOS Local Oxidation of Si

• Use steam or raise furnace pressure to 5 to 10
  atmospheres
• Oxidize create field oxide
• Use etchant to strip away nitride block
• Birds beak -- curved transition region at moat
  edges
• From oxidants diffusing under nitride film

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LOCOS (contd)

• Kooi effect Nitride deposits form underneath pad
  oxide around moat edges
• Cause failure of gate oxide eliminate with
  dummy gate oxidation
• Strip away pad oxide (thinox) grow dummy gate
  oxide in most regions with dry oxidation
• Oxidizes remaining nitride deposits

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Threshold Adjust

• Unadjusted pMOS -1.5 to 1.9 nMOS 0.2 to 0.2
  V
• Change to pMOS 0.7 V (5 V supply)
• Change to nMOS 0.7 V (5 V supply)

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Threshold Adjust Step

• Two ways
• Two separate implants set pMOS Vt and nMOS Vt
• Single Vt adjustment to simultaneously reduce
  pMOS Vt and increase nMOS Vt
• Method
• Implant through dummy gate oxide
• Strip away dummy gate oxide
• Use dry oxidation to grow true gate oxide
• 3V transistor with 100 tox
• Covers channels, sources, drains

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Fabrication Process

• Polysilicon deposition and patterning
• Heavily doped with Phosphorous
• Reduces R to 20 to 40 W /

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Fabrication Process

• Source/Drain Implants
• Implant Arsenic to make n regions
• Implant goes through gate oxide
• Implant Boron to make p regions
• Anneal
• Activates dopants, slightly thicker oxide over
  source drain
• Use high T

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Fabrication Process

• Contacts diffusion poly
• Use multi-level oxide (MLO) to thicken oxide over
  moat areas
• Coat insulate exposed poly
• Allows you to put metal over moats poly without
  rupturing oxide

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Metallization

• Shallow diffusions are susceptible to contact
  spiking
• Use
• Contact silicidation make silicide in contact
  openings
• Refractory barrier metallization
• Put thin film of refractory metal (W, Mo) over
  wafer
• Cover with thicker layer of Cu-doped Aluminum
• Use inter-level oxide (ILO) to insulate between
  metal layers
• Use planarization to minimize steps caused by
  metal 1

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Overglassing

• Mechanical protection and prevents die
  contamination
• Use thick phosphosilicate glass (PSG)

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nMOS Transistor Layout and Cross Section

• Use adjacent source substrate contacts
  (backgate) to improve latchup immunity

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Voltage Ratings

• nFET limits
• Hot e- problem in saturation, charge is
  injected into gate oxide
• Gets trapped cannot remove it
• Ratings
• Blocking voltage rating reflects junction
  breakdown and punchthrough
• Limit for transistors used as switches
  low-frequency digital logic
• Operating voltage rating Analog
• Determined by onset of hot electron degradation
• Applies to transistors that operate most of the
  time in saturation (most analog devices)
• Increasing transistor length
• Reduces effect of hot e-- at drain
• Only get tapped gate oxide charge at drain end

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Natural nMOS Processing

• Block Vt implant to make Vt 0.7 V
• Use when a larger threshold is inconvenient
• pMOS transistors can have hot hole degradation
• Less problematic than hot e-- because of lower mp
• Natural pMOS transistor inconvenient and rarely
  used

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Substrate PNP Transistor

• Collector is p substrate and p epi surrounding
  well
• b is 50 to 100
• Drops if emitter diffusion is silicided (usually
  done)
• Problem Injects current into substrate
• Substrate contacts must be very good
• Collector resistance due to lightly-doped p-epi
  layer
• Between p substrate and p substrate diffusion
  beneath substrate contacts

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Substrate PNP Transistor

• Large substrate contacts are necessary
• Avoids loss of substrate bias voltage
• Contacts must handle 10 to 20 mA substrate current

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Lateral PNP Transistor

• Problems
• No n buried layer (NBL)
• Only small fraction of total emitter current
  reaches collector

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Top View of Lateral PNP
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Analog Transistors Two Design Approaches

• Use large transistors (100 X area of digital
  ones) exactly matched to control circuit behavior
  -- preferred
• Use minimal-sized analog transistors, and totally
  control analog circuit behavior with R, C and L
  ratios

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Benefits of Large Matched Identical Analog
Transistors

• Small random defects dont change matched
  transistors
• Design circuits -- analog transfer function
  depends only on match
• Problems
• Requires large chip area
• DT or diffusion gradients
• May affect one transistor more severely than
  another
• Solution
• Line up transistors with expected gradient so
  both are equally affected
• Diffusion sources, drains need contact strip
  across entire width
• Poly has serious sheet R causes degraded
  operation

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Dual Gate Connection to Poly

• Tie both sides of poly gate to signal with metal 1

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Parallel Transistor Connections

• Many smaller transistors in parallel more
  effective than 1 larger transistor

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Transistor Guard Rings Are Necessary

• p diffusions in p substrate OR
• n diffusions in n-well
• Collect injected minority carriers
• Tie p to VSS
• Tie n to VDD

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p Transistor Guard Ring
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n Transistor Guard Ring
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Substrate Coupling

• Worsens with SoC (system-on-a-chip) integration
• Devices in top of chip inject charge into
  substrate
• Some deeply and to distant circuit elements
• Source of interference

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Substrate Charge Return

• Some charge returns via rear die plate
• Die plate potential varies with charge return
  path impedance
• Cause capacitive coupling to other circuit parts
• Coupling to impedance between ground and die
  plate
• If significant die plate to ground impedance
  injected signal is effectively coupled across the
  chip

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Summary

• Diode physical design
• Bipolar and MOSFET transistor physical design
• Relies on precisely-matched transistors