SPICE Analysis of LowLoss Control ICPower MOSFET Chipset for HighFrequency DCDC Converter Design

1
SPICE Analysis of Low-Loss Control IC-Power
MOSFET Chipset for High-Frequency DC-DC Converter
Design

• Jeff Berwick, John Huang,
• Wayne Grabowski and Richard K. Williams

Siliconix, Inc
Charles Hymowitz and Steve Sandler
Intusoft, Inc
2
Overview

• High frequency power supply design
• Motivation and Challenges
• Methodology Having the right tools for the job
• Selecting a MHz-range MOSFET
• Use of the power loss curve
• Performance of the new Si6801 high speed
  complementary power MOSFET pair

3
Overview (Continued)

• System Modeling in IsSpice
• The new Si9145 controller macromodel
• Detailed modeling example
• Behavioral modeling example
• 1MHz Buck simulation schematic
• Simulation Results
• Startup
• Step Response
• Efficiency
• Conclusions

4
High Frequency Challenges

• Efficiency Decreases
• MOSFET selection is more difficult
• Layout Parasitics are critical
• Measurements are limited
• PC Breadboard modifications are difficult
• Better Design Tools are Needed

5
1MHz SMPS Design Tools

• Power Loss Curve For MOSFET Selection
• Gate Charge and RDSON determine efficiency
• IsSpice For System Design Evaluation
• IsSpice Models for Power FETs, Control IC
• PC Breadboarding for Calibration Tuning

6
Selecting a MOSFET

• Power Switch Loss vs. VGS
• P I2RMS RDS D QG VGS f

7
MOSFET Loss Comparison
8
Si6801 High Frequency MOSFET

• Maximum Gate Bussing Reduces Distributed RG

9
System Modeling in IsSpice

• Power MOSFET Models with accurate QG
• Pulse-by-pulse Controller Model
• Detailed models for output stages
• Behavioral models for digital functions
• Passive Component Models
• Nonlinear Magnetics
• Capacitors with ESR
• PC Board Parasitics R,L,C

10
Si9145 Controller Macromodel
Behavioral Logic
Detailed Output Stage
11
Si9145/Si6801 Pch Switching Speed
12
Hi-Speed Behavioral ModelingSawtooth Oscillator
ICT if (VSW gt Vref/2) then IRT else -IRT
13
Variable Delay Comparator Model
VIN
ABS
DIFFERENCE K(V1 - V2)
VOUT
VARIABLE RES
IDEAL COMPARATOR
14
IsSpice Results Delay vs. O.D.
COMP DELAY vs. OVERDRIVE
/- Overdrive
100mV
10mV
500mV
TIME (SEC.)
15
1MHz Sync Buck Schematic
16
IsSpice Transient Simulation Results

• Measured vs. Simulated
• Startup transient
• Step response
• Steady-state efficiency

17
Si9145 Oscillator Startup
18
300mA Load Step Response
Multilayer Ceramic COUT (25mW ESR)
Vertical 100mV/Div Horizontal 10uS/Div
Tantalum COUT (500mW ESR)
19
Steady-State Efficiency Analysis
20
Simulated Input Power Partitioning

• Power loss vs. Input power _at_ Vin4V

21
Conclusions

• High Frequency shifts design challenge
• MOSFET selection requires RDS and QG
• Parasitics affect performance critically
• Power Loss partitioning depends on ILOAD
• Low ILOAD emphasizes gate loss, bias currents
• High ILOAD emphasizes switch RDS, RWINDING
• Pulse-by-pulse simulation is now practical