IXA Software Framework Programming Model

1
IXA Software Framework Programming Model

• Network Processor Division
• Intel Corporation
• Sept, 2004

2
Agenda

• IXA Software Framework
• Microblock Programming model
• Microblock Architecture
• Dispatch Loop Architecture
• Microblock Groups

3
IXA Software Framework
ExternalProcessors
Control Plane Protocol Stacks
Control Plane PDK
OSSL
XScaleCore Programming Model
Core Components
Core Component Infrastructure Library
Resource Manager Library
Microblock Infrastructure Library
Microengine Programming Model
Micro block
Micro block
Micro block
Utility Library
Protocol Library
Hardware Abstraction Library
4
IXA Software Framework - Goals

• Accelerate software development for the IXP
  family of network processors
• Provide a simple and consistent infrastructure to
  write networking applications
• Enable reuse of components across applications
• Improve portability of code across the IXP family

5
Agenda

• IXA Software Framework
• Microblock Programming model
• Overview
• Components
• Microblock Architecture
• Dispatch Loop Architecture
• Microblock Groups

6
Microengine Programming Model
7
Microblock Programming Model

• Data Plane Libraries
• Libraries for commonly used functions
• Microblock Infrastructure Library
• Used by the Microblocks and the DL to manage
  packet meta data and DL variables
• Microblocks
• Enable development of modular code building
  blocks
• Define the data flow model, common data
  structures, state sharing between code blocks
  etc.
• Ensures consistency and improves reuse across the
  different reference applications
• Dispatch Loop (DL)
• The Glue code that binds Microblocks together to
  form Microblock Group

8
Data Plane Libraries

• Commonly used functions for IXP2XXX Network
  Processor families
• Used by the Microblocks to simplify and speed up
  writing applications
• Available in microcode and Microengine C
• Increase portability of code across IXA network
  processors

9
MicroengineHardware Abstraction Library

• Provides Operating System-like abstraction of
  hardware-assisted functions such as
• Memory and packet buffer freelist management
• Critical section management
• Inter-process communication
• Bus I/O
• Control and Status Registers
• Isolates the developer from changes in future h/w
  implementations

10
MicroengineProtocol and Utility Libraries

• Protocol header field extraction, validation, and
  manipulation for popular protocols (IPv4, IPv6,
  ATM, TCP, UDP)
• Utility functions for buffer management, hash
  table access, CRC computation, Endian swaps, etc.

11
Microblock Infrastructure Library

• A set of macros/functions used by the Microblocks
  and the DL
• Used by the Microblocks to access and modify
• Packet meta data e.g. packet specific
  information
• DL variables state
• Indicate the next processing steps to the DL
• Used by the DL to
• Initialize packet meta data and DL variables
• Read and cache packet header and meta data into
  the Microengine
• Flush packet state and header to memory

12
Microblocks

• A combined set of macros/functions that perform a
  data plane network processing function
• Each Microblock performs a major function on a
  packet
• 5-Tuple Classification, IPv4 Forwarding, NAT
• Written independent of each other
• Reusable across applications
• Use the infrastructure library
• Access and modify packet meta data and DL
  variables
• Use data plane libraries
• Hardware abstraction and code reusability

13
Dispatch Loop

• It is the glue code that combines Microblocks
  together to form a Microblock group
• It is application and implementation specific
• Implementing thread execution order
• Caching Microblock specific data
• Communications between Microengines and XScale
• Order of Microblock execution
• Source and sink packets
• Getting packets (packet descriptor) from the
  previous application stage (over a ring)
• Passing packet to the next application stage
  (over a ring)
• Uses the infrastructure library to
• Cache and flush packet headers and meta data

14
Agenda

• IXA Software Framework
• Microblock Programming model
• Microblock Architecture
• Microblock types
• Microblock structure
• Microblock input/output
• Dispatch Loop Architecture
• Microblock Groups

15
Microblock Architecture
16
Microblock Architecture

• There are two types of Microblocks
• Driver Microblocks
• Packet Processing Microblocks
• Each Microblock consists of two functions
• Initialization macro/function e.g.
  ipv4_fwd_init
• Microblock macro/function e.g. ipv4_fwd
• Microblocks process and modify three types of
  data
• Cached packet segments e.g. packet header
• Packet meta data e.g. packet specific
  information
• DL Variables e.g. Next_Block_ID

17
Microblocks Types
Driver Microblocks
Packet Processing Microblocks
18
Driver Microblocks

• Hardware specific Microblocks
• Receive, Transmit, Queue Manager (QM)
• Interact closely with the hardware features of
  the chip in use
• MSF, Queue Array
• Implementation specific
• RX/TX Ethernet, POS, ATM, CSIX
• QM cell QM, packet QM
• Reside on separate Microengines from packet
  processing Microblocks
• Most likely to be used AS-IS by programmers

19
Packet Processing Microblocks

• Protocol specific Microblocks
• IPv4, IPv6, MPLS, SRTCM
• Implement network processing functions
• 5-Tuple Classification, IPv4 Forwarding, NAT
• Not hardware/processor specific
• Can run on both IXP2400 and IXP2800
• Combine with a DL to form a Microblock group
• PPP Decap, 6-tuple classify, SRTCM, DSCP, IPv4
  fwd
• Classify, IPv-4 forwarding, L2 header
  encapsulation
• May be modified by the programmer to add more
  features to it

20
Microblock Structure

• A microblock consists of two macros/functions
• An initialization macro/function which is called
  once by the DL during startup
• A processing macro/function which is called for
  every packet received
• Example an IPv4 microblock consists of two
  macros
• IPv4_fwd_init
• Initialize the base address for the counters
  maintained by the IPv4_fwd() Microblock function
• Initialize the next hop forwarding table base
• IPv4_fwd
• Execute the specific functions required by the
  protocol to perform IPv4 forwarding

21
Microblock Input and Output

• Each Microblock gets its inputs and produces its
  output by accessing and modifying three data
  structures
• Cached packet segments e.g. packet header
• Packet meta data e.g. packet buffer pointers
• DL variables e.g. Next_Block_ID
• Managed by the infrastructure library
• Cache the data structure from memory (DL)
• Read and write the data structures (Microblocks)
• Flush the data structure back to memory (DL)

22
Cached Packet Header

• DL caches the required packet header segment for
  the Microblock
• Cached header resides in Local Memory or
  registers
• Microblocks read, analyze, and modify the header
  as needed
• DL flushes the header back to memory

23
Packet Meta Data and DL Variables

• Packet meta data
• A data structure that contains packet specific
  information
• Buffer address, buffer size, packet size, input
  port, output port, Next hop ID, flow ID, QoS,
  Queue ID, etc.
• DL variables
• Specify to the DL the path of the packet
  (dl_next_block)
• Microblock on the same Microengine
• The next processing stage on a different
  Microengine
• The XScale core for exception packets
• Dropping the packet
• Hold the exception types and IDs in case of
  exceptions

24
Agenda

• IXA Software Framework
• Microblock Programming model
• Microblock Architecture
• Dispatch Loop Architecture
• Dispatch Loop Structure
• dl_source
• dl_sink
• Microblock Groups

25
Dispatch LoopArchitecture

• Application specific code
• Connects Microblocks with each other to form a
  group
• Caches and flushes packet headers and meta data
• Three main functions
• Source
• Sink
• Microblock execution flow

26
Dispatch Loop Structure in Microcode

• // include files
• include dispatch.uc
• include dl_system.uc
• include IPv4_Fwd.uc
• include l2_encap.uc
• include l2_classify.uc
• Init
• // The following code is
• // executed once
• DL_Source_Init
• IPv4_Fwd_Init
• L2_Classify_Init
• L2_Encap_Init
• DL_Sink_Init

// The following loop runs for // every
packet loop // Get a packet from the Scratch
// Ring DL_Source // Perform Layer-2
Classification // on the packet L2_Classify
// call the IP forwarding block IPv4_Fwd
// Perform Layer-2 Encapsulation L2_Encap
// pass the packet to next // Microengine
DL_Sink BR loop
27
dl_source() function

• System microblock implicit to a DL
• Application specific
• Hides the details of scratch ring interfaces from
  the packet processing Microblocks in the DL
• May be optimized as needed for a specific
  application
• Tasks
• Synchronization with other threads (compile time
  option)
• Read a descriptor from scratch-ring
• Populate packet meta-data cache in GPRs
• Populate IP header cache
• Set DL global variables (dl_buffer_handle)
• Macro/Function name
• dl_source

28
dl_sink() function

• Application specific system microblock implicit
  to a DL
• Tasks
• Flush packet meta data to SRAM
• Queues a descriptor on the scratch ring for the
  next processing stage.
• Flush packet header cache
• Application specific task
• e.g. Computes Queue based on output port and
  class (for Diffserv)

29
Microblock ExecutionFlow

• Code that determines the next Microblock to
  execute based on
• Packet classification
• DL variable dl_next_block
• Some implementations require Microblocks and
  threads to execute in order
• DL calls all the Microblocks for every packet
• Based on dl_next_block
• Microblocks with the same ID will process the
  packet
• Microblocks with a different ID will pass the
  packet to the next Microblock
• Other Implementations do not require the ordering
• DL calls the appropriate Microblock based on
  dl_next_block

30
Microblock Execution Flow
Packet T requires Microblocks a then k
Packet Q requires Microblocks a then z then k
All Microblocks are called
Micro Block m
Micro Blocka
Micro Block f
Micro Block k
Micro Block z
Source
Sink
Only required Microblocks are called by DL
Micro Blocka
Micro Block k
Micro Block z
Source
Sink
Micro Block m
Micro Block f
31
Agenda

• IXA Software Framework
• Microblock Programming model
• Microblock Architecture
• Dispatch Loop Architecture
• Microblock Groups

32
Packet Processing Microblock Group

• Contains Microblocks bounded by a DL
• Key data-structures
• Scratch/NN rings receive packet descriptors from
  previous stage and send them to the next stage
• GPRs Packet meta data and DL variables
• Local Memory Packet header cache
• A Microblock group runs on one thread of one
  Microengine from start to finish
• It can NOT be split over two or more Microengines
• Multiple Microengines/threads can run the same
  Microblock group

33
Packet Processing Microblock Group

• Three Microblocks (Classify, IPv4, Encapsulate)
• One path through the Group

34
Packet Processing Microblock Group
Classify
IPv4
Encap
Source
Sink
. Pull meta-data in GPRs
. Set Header Type to IPv4
. Get DAddr from HCache
. Get DMAC from next-hop N
. Flush HCache to DRAM
. Set DL state in GPRs
. Set next_blk IPv4
. Search Route Table
. Set Eth Hdr in HCache
. Flush meta data to SRAM
. Get Headers in HCache
. Set next-hop-id N
. Queue Handle to Ring
. Set next_blk Classify
. Set next_blk Encap
SRAM
DRAM
Packet Buffer
Route Table
Next Hop Table
Packet Meta Data
Packet Meta Data
IP Header
IP Header
Packet Payload
LM
GPRs
DL Variables Next Block
Class
IPv4
Encap
Class
Encap
IPv4
Source
Sink
35
Questions
36
Backup
37
SDK 3.0 PR-5 Microblocks
x implies it is available in PR-5
38
SDK 3.0 PR-5 Microblocks
x implies it is available in PR-5