ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic Devices

1
ECE2030 Introduction to Computer
EngineeringLecture 20 Datapath and Microcode
Control
Prof. Hsien-Hsin Sean Lee School of Electrical
and Computer Engineering Georgia Tech
2
ISA Implementation

• Putting everything together
• A Datapath Unit
• Register File ? A Collection of Registers
• Operation Control
• Decoding Instruction
• Generating Control Signals to Orchestrate
  Hardware
• Functional Units
• Arithmetic Units
• Logical Units
• Memory Units

3
Register File (32 32-bit Registers)
En
En
Write
Read
4
Register File with Multiple Ports

• Xra X read address
• Yra Y read address
• Xdo X data out
• Ydo Y data out
• Zwa Z write address
• Zdi Z data in
• we write enable
• This register file has
• 2 read ports
• 1 write port
• 32 registers, each 32-bit

5
5
5
Xra
Yra
Zwa
Clock
32
Ydo
RegFile
32
32
Xdo
Zdi
we
5
Adder/Subtractor Unit
32
32
A
B
Carry in
a/s
0 add 1 subtract
AU
En
32
Flags
Carry out
F
Overflow Zero flag
6
Logical Unit
32
32
A
B
LF
4
LU
En
32
F
A B F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A?B
B
A
?
AB
AB
A
AB
AB
B
A?B
7
Logical Unit Bit Slice Implementation
1
0
LF0
0
0
LF1
AnBn
4-to-1 Mux
0
0
LF2
1
1
LF3
An
Bn
8
Logical Unit Bit Slice Alternative
Bn
An
0
LF0
1
4-to-16 Decoder
6
LF1
LF2
LF3
15
Fn
9
Shift Unit

• B shift amount
• Shift Type (ST)
• 00 no shift
• 01 logical shift
• 10 arithmetic shift
• 11 rotate
• Shift Direction (SD)
• 0 left
• 1 right

32
32
A
B
2
ST
SU
En
SD
32
F
10
Combined with Register File
5
5
5
Xra
Yra
Zwa
Clock
Ydo
RegFile
32
Xdo
Zdi
we
32
32
A
B
Cin
a/s
AU
En
32
Flags
Cout
11
Single Cycle Datapath
5
5
5
Xra
Yra
Zwa
Clock
32
Ydo
RegFile
32
32
Xdo
Zdi
we
A
B
A
B
A
B
Cin
a/s
LF
ST
AU
LU
SU
En
SD
Flags
Cout
32
12
Arithmetic and Logic Unit (ALU)
A
B
A
B
A
B
Cin
a/s
LF
ST
AU
LU
SU
En
SD
Flags
Cout
32
32
A
B
a/s
00 AU 01 LU 10 SU 11 disable ALU
2
4
LF
ALS
2
ALU
ST
SD
I omit some input/output e.g. carry, flags etc.
13
Single Cycle DataPath
5
5
5
Xra
Yra
Zwa
Clock
Ydo
RegFile
32
Xdo
Zdi
we
32
32
A
B
a/s
2
4
LF
ALS
2
ALU
ST
SD
32
14
DataPath with Immediate Input
Sign-extended immediate
Immediate Enable
5
5
5
32
1
Xra
Yra
Zwa
Clock
32
0
Ydo
RegFile
32
32
Xdo
Zdi
we
32
32
A
B
a/s
2
4
LF
ALS
2
ALU
ST
SD
32
15
DataPath with Memory
Sign-extended immediate
msel
5
5
5
32
Xra
Yra
Zwa
1
32
Clock
Memory
Ydo
0
RegFile
32
32
Xdo
Address
Zdi
we
32
32
A
B
a/s
4
2
LF
ALS
ALU
ST
2
SD
32
Data
load Z, (X)
store Y, (X)
16
Instruction Execution

• Instruction Fetch
• Given a PC address
• Retrieve instruction from memory (or cache)
• Instruction Decode
• Instruction type, operands, etc.
• Control signals
• Instruction Execute
• Functional unit binding
• Instruction Complete
• Writeback to register or memory
• Can be done in single cycle or multiple cycles
• Instruction complexity (CISC vs. RISC)
• Pipelining

17
Microcode Sequencer

• For a multi-cycle implementation or a CISCy ISA
• Think about an x86 string copy instruction
• An ISA instruction is translated into several
  microinstructions or microcode
• These microinstructions
• One per cycle
• Harness the detailed signals inside a processor
• Define low-level control signals in a given state
• Microcode Sequencer
• A finite state machine
• Generate microinstruction sequence
• Most of RISC instructions is one-to-one mapping
• Could be implemented as a ROM or a PLA

18
Microcode Memory
Datapath Control Signals
Microcode Memory (ROM or PLA) Combinational Logic
Needed for a multi-cycle instruction
implementation
State register
Instruction Register
19
Microcode Memory
Datapath Control Signals
Microcode Memory (ROM or PLA) Combinational Logic

• Our Single-Cycle Microcode Memory
• Assume all steps finish within one cycle
• No state needed
• Not really a microcode sequencer

Instruction Register
20
A Simple Processor
Instruction Register
X
5
Y
5
Z
5
imm
16
Memory
imm_en
we
Microcode Memory (Single-Cycle Implementation)
ALS
2
Single Cycle Datapath
a/s
LF
4
ST
2
SD
ld_en
st_en
?/w
msel
21
A Simple Processor
add 4, 3, 2
31
26
25
21
20
16
15
11
10
6
5
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
rs
opcode
rt
rd
shamt
funct
X00011
Y00010
Z00100
imm0
Memory
imm_en0
we1
Microcode Memory
ALS00
Single Cycle Datapath
a/s0
LF0000
ST00
SD0
ld_en0
st_en0
?/w0
msel0
22
Datapath Control Signals
Sign-extended immediate
imm enable
msel
st enable
5
5
5
32
Xra
Yra
Zwa
1
32
Clock
Memory
Ydo
0
RegFile
32
32
Xdo
Address
Zdi
we
32
32
A
B
a/s
2
00 AU 01 LU 10 SU 11 Disable ALU
4
LF
ALU
ALS
ST
2
SD
32
Data
Logical Flag 0001 AND 0011 A 0101 B 0110
XOR 0111 OR
ld enable
Shift Type (ST) 00 No Shift 01 Logical 10
Arithmetic 11 Rotate
Shift Direction (SD) 0 Left 1 Right
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Microcode Control (1)

• Clear memory location 100, 104 (r0 hardwired
  to 0)

Datapath Control Signals
?instruction sequence X (5) Y (5) Z (5) we Imm_en Imm_val ALS a/s LF ST SD ld_en st_en ?/w msel
li r1,100
sw r0, (r1)
addi r1,r1,4
sw r0, (r1)
ALS 00 AU 01 LU 10 SU 11 Disable ALU
Shift Type (ST) 00 No Shift 01 Logical 10
Arithmetic 11 Rotate
Shift Direction (SD) 0 Left 1 Right
Logical Flag (LF) 0001 AND 0011 A 0101 B 0110
XOR 0111 OR
24
Microcode Control (1)

• Clear memory location 100, 104 (r0 hardwired
  to 0)

?instruction sequence X (5) Y (5) Z (5) we Imm_en Imm_val ALS a/s LF ST SD ld_en st_en ?/w msel
li r1,100 x x 00001 1 1 0x0064 01 x 0101 x x 0 0 x 0
sw r0, (r1) 00001 00000 x 0 0 x 11 x x x x 0 1 1 1
addi r1,r1,4 00001 x 00001 1 1 0x0004 00 0 x x x 0 0 X 0
sw r0, (r1) 00001 00000 x 0 0 x 11 x x x x 0 1 1 1
ALS 00 AU 01 LU 10 SU 11 Disable ALU
Shift Type (ST) 00 No Shift 01 Logical 10
Arithmetic 11 Rotate
Shift Direction (SD) 0 Left 1 Right
Logical Flag (LF) 0001 AND 0011 A 0101 B 0110
XOR 0111 OR
25
Microcode Control (2)

• copy 4-byte data from 0xF000 to 0xA100
• clear data at 0xF000

?instruction sequence X (5) Y (5) Z (5) we Imm_en Imm_val ALS a/s LF ST SD ld_en st_en ?/w msel
li r5, 0xF000
lw r6, (r5)
li r7, 0xA100
sw r6, (r7)
sw r0, (r5)
ALS 00 AU 01 LU 10 SU 11 Disable ALU
Shift Type (ST) 00 No Shift 01 Logical 10
Arithmetic 11 Rotate
Shift Direction (SD) 0 Left 1 Right
Logical Flag (LF) 0001 AND 0011 A 0101 B 0110
XOR 0111 OR
26
Microcode Control (2)

• copy 4-byte data from 0xF000 to 0xA100
• clear data at 0xF000

?instruction sequence X (5) Y (5) Z (5) we Imm_en Imm_val ALS a/s LF ST SD ld_en st_en ?/w msel
li r5, 0xF000 X X 00101 1 1 0xF000 01 X 0101 X X 0 0 X 0
lw r6, (r5) 00101 X 00110 1 0 X 11 X X X X 1 0 0 1
li r7, 0xA100 X X 00111 1 1 0xA100 01 X 0101 X X 0 0 X 0
sw r6, (r7) 00111 00110 X 0 0 X 11 X X X X 0 1 1 1
sw r0, (r5) 00101 00000 X 0 0 X 11 X X X X 0 1 1 1
ALS 00 AU 01 LU 10 SU 11 Disable ALU
Shift Type (ST) 00 No Shift 01 Logical 10
Arithmetic 11 Rotate
Shift Direction (SD) 0 Left 1 Right
Logical Flag (LF) 0001 AND 0011 A 0101 B 0110
XOR 0111 OR
27
Microcode Control (3)

• Perform r2 5?(r2 2r3) 3r4
• store r2 to location stored in r10

?instruction sequence X (5) Y (5) Z (5) we Imm_en Imm_val ALS a/s LF ST SD ld_en st_en ?/w msel
sll r3, r3, 1
sub r2, r2, r3
sll r5, r2, 2
add r2, r5, r2
sll r6, r4, 1
add r4, r6, r4
add r2, r2, r4
sw r2, (r10)
ALS 00 AU 01 LU 10 SU 11 Disable ALU
Shift Type (ST) 00 No Shift 01 Logical 10
Arithmetic 11 Rotate
Shift Direction (SD) 0 Left 1 Right
Logical Flag (LF) 0001 AND 0011 A 0101 B 0110
XOR 0111 OR
28
Microcode Control (3)

• Perform r2 5?(r2 2r3) 3r4
• store r2 to location stored in r10

?instruction sequence X (5) Y (5) Z (5) we Imm_en Imm_val ALS a/s LF ST SD ld_en st_en ?/w msel
sll r3, r3, 1 00011 X 00011 1 1 0x0001 10 X X 01 0 0 0 X 0
sub r2, r2, r3 00010 00011 00010 1 0 X 00 1 X X X 0 0 X 0
sll r5, r2, 2 00010 X 00101 1 1 0x0002 10 X X 01 0 0 0 X 0
add r2, r5, r2 00101 00010 00010 1 0 X 00 0 X X X 0 0 X 0
sll r6, r4, 1 00100 X 00110 1 1 0x0001 10 X X 01 0 0 0 X 0
add r4, r6, r4 00110 00100 00100 1 0 X 00 0 X X X 0 0 X 0
add r2, r2, r4 00010 00100 00010 1 0 X 00 0 X X X 0 0 X 0
sw r2, (r10) 01010 00010 X 0 0 X 11 X X X X 0 1 1 1
ALS 00 AU 01 LU 10 SU 11 Disable ALU
Shift Type (ST) 00 No Shift 01 Logical 10
Arithmetic 11 Rotate
Shift Direction (SD) 0 Left 1 Right
Logical Flag (LF) 0001 AND 0011 A 0101 B 0110
XOR 0111 OR
29
Instruction Fetching (PC Update)
Next PC generation
32
addr
Program Counter
Memory
32
Instruction Register
data
32x32 RegFile
Microcode ROM
Datapath
30
Sequential Instruction Fetch
4

32
addr
Program Counter
Memory
32
Instruction Register
data
32x32 RegFile
Microcode ROM
Datapath
31
Branch Support
Offset (from ?ROM)
4
ext
beq bne (if true)
0
1
mux

32
addr
Program Counter
Memory
32
Instruction Register
data
32x32 RegFile
Microcode ROM
Datapath
32
Branch and Jump Support
Offset (from ?ROM)
rs
4
ext
Target addr (from ?ROM)
beq bne (if true)
0
1
mux
ext

0
1
mux
jr
0
1
mux
j
32
addr
Program Counter
Memory
32
Instruction Register
data
32x32 RegFile
Microcode ROM
Datapath