FPGA2000 - Field Programmable port Extender (FPX) for Distributed Routing and Queuing

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Using the SDRAM Controller on Field Programmable
Port Extender (FPX)
Sarang Dharmapurikar Washington University,
Applied Research Lab August 15, 2001 Supported
by NSF ANI-0096052 and Xilinx Inc. http//www.ar
l.wustl.edu/arl/projects/fpx
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SDRAM Controller Overview
SDRAM Controller
Module 0
SDRAM
Module 1
Module 2
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SDRAM Controller Features

• Arbitrates between multiple memory requests
• Maintains sequential consistency for each module
• Maximizes the SDRAM throughput by
• - Re-ordering memory requests based on
  addresses and
• operation type
• - Favoring the locality in memory access
• Increases throughput for higher locality

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SDRAM controller performance
Effect of locality on the SDRAM data bus
utilization
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SDRAM Controller Usage
Request
Request(n)
Grant1
Grant1(n)
Grant2
Grant2(n)
InfoBus
InfoBus
To SDRAM
DataBus
DataBus
SDRAM Controller
Module n
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Protocol
Data Transaction
Make Request
Wait Grant1
yes
Grant1?
No
Grant2?
No
yes
Send Address
Send Burst Length Send Op Type
Wait Grant2
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Write Timing
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Read Timing
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Example Leaky Bucket
bursty data
leaking data

• What does it do?
• - Buffers the incoming cells in a FIFO
• - Generates tokens at a regular interval
• - Gives out a cell from the FIFO when the
  number of tokens gt 0
• - Destroys a token when a cell is given out

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Example Leaky Bucket Implementation
SDRAM
SDRAM Controller
Send Cell
Pull Cell
Push Cell
Get Cell
Cell FIFO
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Example Leaky Bucket Testbench
CELLOUT.DAT
TESTCELL.DAT
Fake_nid_out
Fake_nid_in
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Exercise

• Take a walk through Leaky Bucket
• Wire up Cell FIFO in Leaky Bucket
• Wire up Leaky Bucket, SDRAM controller in
  test-bench
• Change the parameters
• - c_MaxTokenCount
• - c_PaceInterval
• Try different traffic patterns and verify the
  Leaky Bucket functionality