CPSC 161 Lecture 3

1
CPSC 161Lecture 3

• Prof. L.N. Bhuyan
• http//www.cs.ucr.edu/bhuyan/

2
Review of MIPS Instruction Formats

• simple instructions all 32 bits wide
• very structured, no unnecessary baggage
• only three instruction formats

op rs rt rd shamt funct
R I J
op rs rt 16 bit address
op 26 bit address
3
MIPS Instructions
R-format
I- format
I-format
lt- R-format
lt- J-format
lt- R-format
lt- J-format
4
Assembly Operands Registers

• Naming of 32 MIPS registers instead of r0, r1,
  , r31, use
• s0, s1, for registers corresponding to C
  variables
• t0, t1, for registers corresponding to
  temporary variables
• Will explain mapping convention later of s0,
  s1, , t0, t1, , to r0, r1,
• Note whereas C declares its variables (e.g., int
  fahr), Assembly operands (registers) are fixed
  and not declared

5
Policy of Use Conventions
6
Role of Registers vs. Memory

• What if more variables than registers?
• Compiler tries to keep most frequently used
  variables in registers
• Writing less common to memory spilling
• Why not keep all variables in memory?
• Smaller is faster registers are faster than
  memory
• Registers more versatile
• MIPS arithmetic instruction can read 2, operate
  on them, and write 1 per instruction
• MIPS data transfer only read or write 1 operand
  per instruction, and no operation

7
Compilation using Registers

• Compile by hand using registersf (g h) -
  (i j)
• Register Allocations f s0, g s1, h s2,
  i s3, j s4
• MIPS Instructions
• add s0,s1,s2 s0 gh
• add t1,s3,s4 t1 ij
• sub s0,s0,t1 f(gh)-(ij)

8
MIPS Instruction Encoding

• Examples of some Opcodes
• Instruction Format Opcode shamt
  funct
• Add R 0
  0 32
• Sub R 0
  0 34
• Shift (by 4) R 0
  4 0
• Add (imm) I 8
  n.a n.a
• Lw (load word) I 35
  n.a n.a
• Sw (store word) I 43
  n.a n.a

9
Data Transfer Instruction Memory to Reg

• Load moves data from memory to register
• Syntax
• 1) operation name
• 2) register to be loaded
• 3) constant and register to access memory
• MIPS name, lw for load word
• Example lw t0, 8(s3)

Called offset
Called base register
or base address register or base address
10
Compilation when Operand is in Memory

• Q Compile by hand using registers g h
  A300 gs1, hs2, s3starting (base)
  address of array A
• Since A300 is in memory, 1st transfer from
  memory to (temporary) register
• lw t0,300(s3) Adds 300 to s3 to select
  A300, puts into t0
• lw t0,1200(s3) For byte addressable machines
  300x4
• Next add it to h and place in g
• add s1,s2,t0 s1 hA300
• HW Compile A300 h A300

11
Tanslating to MIPS Machine Language

• From the instruction set, Opcode for Lw is 35.
  Opcode for add is 0 with funct 32.
• From register assignment table, t08, s117,
  s218 and s319.
• Instruction consists of op5 bits, rs5bits,
  rt5bits, rd5bits, shamt5bits and funct6bits
  for R format and address16 bits instead of
  rd,shamt and funct for I format total32 bits
• Assembly language lw t0, 1200(s3) and add
  s1,s2,t0 translate to
• --------------------------------------------------
  -------------------------
• op rs rt rd address/shamt
  funct
• 35 19 8 1200
  
• 0 18 8 17 0 32
  

12
Compile with variable index

• What if array index not a constant? g h
  Ai
• gs1, hs2, is4, s3base address of A
• To load Ai into a register, first turn i into a
  byte address multiply by 4
• How multiply using adds?
• i i 2i, 2i 2i 4i
• add t1,s4,s4 t1 2i
• add t1,t1,t1 t1 4i

13
Compile with variable index, cont

• Next add to base of A
• add t1,t1,s3 t1address of Ai
  (4is3)
• Now load Ai into a temporary register
• lw t0,0(t1) Temp t0 Ai
• Finally add to h and put sum in g
• add s1,s2,t0 g h Ai

14
MIPS arithmetic instructions

• Instruction Example Meaning Comments
• add add 1,2,3 1 2 3 3 operands
• subtract sub 1,2,3 1 2 3 3 operands
• add immediate addi 1,2,100 1 2 100
  constant
• add unsigned addu 1,2,3 1 2 3 3
  operands
• subtract unsigned subu 1,2,3 1 2 3 3
  operands
• add imm. unsign. addiu 1,2,100 1 2 100
  constant
• multiply mult 2,3 Hi, Lo 2 x 3 64-bit
  signed product
• multiply unsigned multu2,3 Hi, Lo 2 x
  3 64-bit unsigned product
• divide div 2,3 Lo 2 3, Lo quotient, Hi
  remainder
• Hi 2 mod 3
• divide unsigned divu 2,3 Lo 2
  3, Unsigned quotient remainder
• Hi 2 mod 3
• Move from Hi mfhi 1 1 Hi Used to get copy of
  Hi
• Move from Lo mflo 1 1 Lo Used to get copy of
  Lo

Which add for address arithmetic? Which add
for integers?
15
MIPS logical instructions

• Instruction Example Meaning Comment
• and and 1,2,3 1 2 3 3 reg. operands
  Logical AND
• or or 1,2,3 1 2 3 3 reg. operands
  Logical OR
• xor xor 1,2,3 1 2 Å 3 3 reg. operands
  Logical XOR
• nor nor 1,2,3 1 (2 3) 3 reg. operands
  Logical NOR
• and immediate andi 1,2,10 1 2 10 Logical
  AND reg, constant
• or immediate ori 1,2,10 1 2 10 Logical OR
  reg, constant
• xor immediate xori 1, 2,10 1 2
  10 Logical XOR reg, constant
• shift left logical sll 1,2,10 1 2 ltlt
  10 Shift left by constant
• shift right logical srl 1,2,10 1 2 gtgt
  10 Shift right by constant
• shift right arithm. sra 1,2,10 1 2 gtgt
  10 Shift right (sign extend)
• shift left logical sllv 1,2,3 1 2 ltlt 3
  Shift left by variable
• shift right logical srlv 1,2, 3 1 2 gtgt 3
  Shift right by variable
• shift right arithm. srav 1,2, 3 1 2 gtgt 3
  Shift right arith. by variable

16
MIPS data transfer instructions

• Instruction Comment
• SW 500(R4), R3 Store word
• SH 502(R2), R3 Store half
• SB 41(R3), R2 Store byte
• LW R1, 30(R2) Load word
• LH R1, 40(R3) Load halfword
• LHU R1, 40(R3) Load halfword unsigned
• LB R1, 40(R3) Load byte
• LBU R1, 40(R3) Load byte unsigned
• LUI R1, 40 Load Upper Immediate (16 bits shifted
  left by 16)

LUI R5
0000 0000
R5
17
Section 2.6 MIPS decision instructions

• Decision instruction in MIPS
• beq register1, register2, L1
• beq is Branch if (registers are) equal Same
  meaning as (using C) if (register1register2)
  go to L1
• Complementary MIPS decision instruction
• bne register1, register2, L1
• bne is Branch if (registers are) not equal
  Same meaning as (using C) if
  (register1!register2) go to L1
• Called conditional branches

18
Compiling C if into MIPS Summary

• Compile by hand
• if (i j) fgh else fg-h
• Mapping f s0, g s1, h s2, i s3, j s4
• beq s3,s4, True branch ij sub
  s0,s1,s2 fg-h(false) j Exit go
  to ExitTrue add s0,s1,s2 fgh
  (true)Exit
• Note Compiler supplies labels, branches not
  found in HLL code often it flips the condition
  to branch to false part

C
MIPS
19
Loops in C/Assembly Summary

• Loop g g Ai i i j if (i ! h)
  goto Loop
• (g,h,i,js1,s2,s3,s4 base of As5)
• Loop add t1,s3,s3 t1 2i add
  t1,t1,t1 t1 4i add t1,t1,s5
  t1addr A lw t1,0(t1) t1Ai add
  s1,s1,t1 ggAi add s3,s3,s4 ii
  j bne s3,s2,Loop goto Loop if
  i!h

C
MIPS
20
Branch Addressing PC-relative

• Conditional Branch beq t0,t1,label
• address just 16 bits (216), program too small!
• Option always add address to a register PC
  Register Branch address
• Change register contents gt bigger programs
• Which register?
• How use conditional branch? if-else, loops
• Near current instruction gt use PC as reg!
• PC-relative addressing (PC4) /- 215 words

I
6 bits
5 bits
5 bits
16 bits
21
Branch Addressing Jumps, J format

• j label go to label
• j has only one operand add format
• large address allows large programs
• bright idea address of instruction always
  multiple of 4 (instructions always words) gt
  store number of word, save 2 bits
• Example j exit exit 10000
• PC address 4 upper 4 bits of old PC

J
6 bits
26 bits
J
22
Branch Addressing PC-relative Example

• Loop slt t1,zero,a1 t19,a15
  beq t1,zero,Exit nogtExit
  add t0,t0,a0 t08,a04 subi a1,a1,1
  a15 j Loop goto Loop Exit add
  v0,t0,zero v02,t08

Set t11 if zero lt a1
Address
0
5
9
0
4
9
0
3
8
4
8
0
8
5
5
-1
2
20000
8
0
2
0