How to Make Efficient Communication, Collaboration, and optimization from System to Chip

1
How to Make Efficient Communication,
Collaboration, and optimization from System to
Chip

• Akira Matsuzawa
• Tokyo Institute of Technology
• (Matsushita Electric Ind., Co. before this April)

2
Contents

• Issues of current SoC development
• Solutions
• Case study Development of Mixed signal SoC
• Summary

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System DVD player
Current electrical system is complicated and
needs analog and memory.
32bit MCU DRAM Embedded
Optical Disc
Optical Head
Media Core Processor
Memory
16M SDRAM
Red Laser
MPEG Algorithm
Photo-receptive Compound
4M DRAM
Head Amp
Driver
Red Laser Unit
MPEG 2 Video
AV Decoder
Video Output
High-speed Analog-Digital
ODC
Copy Protection
Read Channel
Demodulation ECC
AC-3 Output
AC-3 Audio
Pre Amp
Analog
CD DEM
Stereo Output
Analog Front End
System Controller MCU
Servo DSP
Console Panel
Servo DSP
System Controller MCU
First-Gen.
Third-Gen.
OS API
Second-Gen.
Fourth-Gen.
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Super one-chip SoC for DVD
This SoC integrates analog FE, font-end, and
back-end in 0.13um tech.
24M Tr
ISSCC 2003, K Okamoto et., al.
Analog
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Narrow development time slot
Development time slot is very narrow. Just in
time develop is required.
12 Mon
12 Mon
3 Mon
6 Mon
6 Mon
12 Mon
Combo
Combo
16x DVD ROM
12x DVD ROM
Sales (A.U)
8x DVD ROM
6x DVD ROM
2nd G 2.6G RAM
First DVD ROM
4.7G RAM
2.6G RAM
97
00
Time
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Choice of transistor
A variety of transistor has increased.
Choose the proper transistor depending on the
systems
5V
3V
2.5V
1.8V
1V
1.2V
1.5V
100
Operating Voltage (V)
Low leak (3pA/um)
50
Constant VT
Delay time (Arbitral)
Middle leak (1nA/um)
10
Scaled VT
5
Constant Vt/VDD
0.1
1.0
0.2
0.3
0.5
Design rule (um)
7
Scaled CMOS
Current Scaled Si technology is very artistic.
How to control it and how to increase the
production yield quickly!
Gate
Seven lattices
SiO2
Si
100nm
Transistor
Interconnection
8
Library choice
Which library realizes the smallest area with
enough speed?
9
Mixed signal technology
Mixed signal is vital to current SoC for Consumer
and networking.
However, conventional analog needs 2 or 3
redesign!
How to develop it without re-design!
Data In (Erroneous)
Data Out (No error)
10
Unified development groups
A Unification of different technology groups is a
key for success.
System Tech.
Architecture tech.
Design tech.
Software tech.
Collaboration
Collaboration
Unification Optimization
Process tech.
LSI design tech.
Memory tech.
Nano-fab tech.
Mixed signal tech.
Device tech.
Low power tech.
Package tech.
EDA tech.
Collaboration
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Overlapped groups for seamless development
Conventional development style took long
development time and always had many problems on
the boundary.
Solve the boundary problems by collaboration!
0.35um era
0. 13um era
System
System
Design
Design
Process
Process
Past issues
Product
Takes longer time
Product
Problems on the boundary
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System target driven development
System target driven can reduce unconformities
and shorten the TAT.
Conventional
System target.
Unconformity
Process dev.
Spec. Cost and Time
Cell Lib. Dev.
SoC design
Design modif.
MP
Process modif.
System target
Advanced
System driven!
Process dev.
Collaboration
to solve boundary problems
Cell Lib. Dev.
Shorten dev. TAT
SoC design
MP
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Making roadmap
Making roadmap makes good communication and
corroboration Between different groups.
Mixed signal Clocking Power routing
Cell height HP Analog HP I/O
Mixed signal Large systems verification
SoC Design
Cell Lib.
System
Reliability High Idd Low Ioff
EMI sim Cross-talk sim Mixed signal sim
Making roadmap and meetings
Device
EDA
Test
Process
Iddq test Wafer burn-in Mixed signal
Low-k Cu STI Analog
Package
Fab
High yield Quick ramp-up Analog control
POE Low inductance
Future demand
Quick parameter extraction
Future issues and tradeoffs
Solutions
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Bidirectional design flow
Bidirectional design flow feed forward flow, as
well as feedback flow can pass early targets to
different groups. This shorten the TAT and reduce
the conflicts.
Feed back (Conventional)
Feed forward (Advanced)
System
Speed
SoC Design
Delay
Cell Lib.
Target flow
Verification Flow
Ids
Device
L, Tox
Process
Yield
Product
15
Modeling and simulation
Collaboration should be done with
simulators. Making good model and simulator will
make our core-competence.
Chip design
Library/ Circuit
Device
To process
From system
Target
Target
Simulator N
Simulator N1
Simulator N-1
Tpd
Ids
Tox, L, VT
Verify
Verify
Quick iteration
Quick iteration
lt8
Planning stage Very quick with enough accuracy
Sensitivity analysis
Optimize between
trade-offs
Model development!
Final stage Quick with high accuracy
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Modularization
Modularize the process and set the each target.
Shorten TAT and easy to find the issue.
Conventional
Full process validation
Advanced
Well
Module validation Full process validation
STI
STI
Isolation
Serial to Parallel!
Transistor
STI
STI
Isolation
Transistor
Contact
Wire
Contact
STI
STI
Wire
Short loop TEG (Check Electrical chara. yield)
STI
STI
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Hardware emulator
System perfection is a basis of whole
development. Hardware emulator can shorten TAT
and increase design quality.
Performance. Analysis SES/Work Bench
SoC Model
Video I/O
Hardware Emulator
System Verification Cadence/SPW
LCD
Image I/O device
Real chip
CPU chip
Real system
Virtual system
Co verification CoWare/N2C
Emulator
Emulation QuickTurn/ MercuryCoBALT
Target board
Eva board
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Strategy for the mixed signal SoC

• System design
• Digital calibration for analog adjustment and
  unknown parameters.
• System optimization to reduce analog area and
  increase robustness.
• System verification
• Fast and accurate mixed signal system simulator
  with behavioral model to verify and optimize the
  mixed signal system.
• Create the target performance for circuit blocks.
• Circuit design
• Ultra fast and accurate circuit simulation for
  P.V.T and fluctuation analysis to verify the
  performance and robustness.
• Circuit optimizer to find the sweet spot of the
  circuit.
• Automated creation of analog behavioral model for
  system sim.
• Process and device development
• Develop suitable analog option device
• Early analog parameter extraction ( mismatch,
  temp. and voltage chara.)
• Monitor and control the analog parameters in Fab.

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Design flow for mixed signal SoC
Design flow from System to layout with top down
and bottom up process should be used for
designing mixed signal SoC. Accurate and a
variety of device parameters is an another key.
Unified design flow controller
Device parameters (SPICE, Noise, Mismatch)
Bottom up flow
System design (Mixed signal level)
Actual Circuit model
Transistors Passives Substrate Package Cable
Required SPEC
Top down flow
Circuit design (SPICE Behavioral)
Optimizer
Parasitic effect
Layout design (Semi/Full automated)
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Mixed signal system design
Needs mixed signal Simulation for total signal
processing.
Many parameters and processing methods should be
optimized.
Real disc signal
Encoder/Decoder Methods
ENCODER
Analog
Digital
Resolution
BER
Processing Method
of Taps
of Taps
of Path
Boost level
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Mixed signal system simulation
Mixed signal system should be verified and
optimized. Circuit spec should be determined by
M/S system simulation.
ADC resolution effect
RLL (2, 10) recorded data
4b
PR(3,4,4,3) waveform
BER
5b
Viterbi decoded result
6b
7b
SNR
System verification
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Mixed language simulation
Mixed language Sim. is 56x faster than SPICE with
same accuracy. This will contribute to short
design TAT and high design quality.
Verilog-AVerilod-D SPICE
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Unified mixed signal design system
New design system increases design speed, 10x to
50x. This also contributes design quality. PVT
simulation is available in acceptable time.
Design flow controller
Optimization
System level
Specification
Simulation Results
Documentation Test bench PVT analysis Spec
sheet Behavioral model Optimization Simulation
flow
Verilog-AMS SPICE
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Controller for automated simulation
Simulation process should be controlled
automatically.
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LSI design using behavioral model
Example Analog Front End chip for ADSL system.
LNA
Output driver
Buffer
Buffer
Filter
Filter
D/A
A/D
VCXO cont.
Control logic
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Hierarchical and behavioral system design
System should be described in behavioral
language, hierarchically.
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Virtual System test using verilog AMS and Matlab
We can simulate the performance of mixed signal
system, using Verilog AMS and Matlab.
Matlab DMT modulation
Matlab DMT demodulation
Constellation DEC
FIR
IFFT
Constellation ENC
FIR
FFT
Matlab is used as a soft DSP
gt 66dB
Q
I
f
QAM constellation
MTPR TEST (DMT Carrier hole)
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Fitting between behavioral and Spice
The combination Verilog AMS and SPICE assures
system level perfection.
Circuit should be designed based on
system-verified spec.
Function check In Verilog-AMS
Verilog-A
Verilog-A Sim
Specification
Circuit design (SPICEVerilog AMS)
Fitting check
SPICE
SPICE sim
Behavioral model extraction
If needed
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Cost up issue by analog I/O
Cost of mixed signal LSI will increase when using
deep sub-micron device, due to non-scalable
analog and I/O parts.
Large analog on SoC must be unacceptable in near
future.
Wafer cost increases 1.3x for one generation
I/O
Analog
(0.35um 1)
Digital
Chip area
Chip cost
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Scaled analog and M/S compensation
Use scaled transistors and not accurate
passives. Address the issues by MS compensation
and system optimization.
0.35um Tr Accurate passive
0.18um_0.13um Tr Not accurate passive
Pros
Small area (low cost) High speed Low power
(If low Vdd is acceptable)
Cons
Low accuracy Sensitive to Process Large 1/f
noise
Solution
Analog compensation Digital calibration
System optimization
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Digital calibration in M/S SoC for DVD
Analog is calibrated by digital
automatically. This becomes practical. SoC has
CPU and digital area becomes smaller.
Collaboration make it possible!
Solve digital issue by analog, and analog issue
by digital.
Analog Filter output
RF input
Extracted Data
Level Detector
LMS
Offset Adjust
5th order Gm-C Filter
FIR Filter
Viterbi Detector
7bit ADC
VGA
FIR output
digital control
Frequency Phase Comparator
Pick up Outputs
Loop Filters
Offset Control
DAC
Digital Calibration
Analog Buffers
Gain Control
DAC
DACs

VCO
Defect Detect
Wobble Filter
Wobble Detect
1/N
Servo Pre-Processor
Extracted Clock
Clock Control
System Clocks
...
Defect
Servo Error Signals
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Summary

• Current SoC development has many issues.
• System complexity
• Device and process complexity, large variety
• Narrow development time slot, huge development
  cost
• Solution must be making collaboration and
  optimization from system to chip.
• Unified and overlapped development groups
• Making roadmap and bidirectional design flow.
• Modeling and simulation system
• Mixed signal SoC as an example.
• Bidirectional design flow
• System simulator and behavioral modeling
• Unified design system with simulation controller