Equalization

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Equalization Clock Recovery for a 2.5-10 Gb/s
2PAM/4PAM Backplane Transceiver Cell

• May 2, 2003
• Fred Chen
• Sr. Member of Technical Staff
• Rambus Inc.

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Agenda

• The Backplane Environment
• PAM2 vs. PAM4 signaling
• Link Design
• Simulation Measured Results
• Conclusions

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The Backplane Environment

• There are many sources of Z and thus many
  possible sources of reflections
• Board Material Loss
• Counter Bored Backplane Vias

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Backplane Component Effects
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Variations Within a Backplane

• Four channels from a single FR4 backplane
• There are large variations between channels

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Single Bit Response

• Iimpact of reflections increases when relative to
  equalized eye
• Wworst-case sequence can sum all reflections

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Reflection Sources

• Primary reflection sources are at the
  connector/backplane transition
• Grouped in time as a function of backplane
  length

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(left) 2-PAM probability distribution function
(PDF) showing the probability of an eye waveform
for each voltage at the sample point (right)
equalized eye with worst-case pattern. 6.4Gb/s
over 20 backplane.
Eye With Worst Case Reflections
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Agenda

• The Backplane Environment
• PAM2 vs. PAM4 signaling
• Link Design
• Simulation Measured Results
• Conclusions

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What is 4-PAM

• Binary (NRZ) is 2-PAM
• 2-PAM uses 2-levels to send one bit per symbol
• Signaling rate 2 x Nyquist

• 4-PAM uses 4-levels to send 2 bits per symbol
• Each level has 2 bit value
• Signaling rate 4 x Nyquist

Note both can be either single-ended or
differential
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When Does 4-PAM Make Sense?

• First order slope of S21
• 3 eyes 1 eye 10db
• loss gt 10db/octave 4-PAM should be considered

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Agenda

• The Backplane Environment
• PAM2 vs. PAM4 signaling
• Link Design
• Equalization
• Clocking
• Simulation Measured Results
• Conclusions

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Equalization For Loss Flatten Response

• Channel is band-limited
• Equalization boost high-frequencies relative to
  lower frequencies

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Transmit Linear Equalizer SBR
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Transmit and Receive Equalization

• Transmit and receive equalizers are combined to
  make a range restricted DFE
• Tx equalizer functions as the feed-forward filter
• Rx equalizer restricted in performance of loop

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Tx Rx Equalization Ranges
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2-PAM/4-PAM Transmitter

• Transmit either 2-PAM or 4-PAM using Gray code

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5-Tap 2P/4P Transmitter (Original)

• Simple 2P/4P transmitter Total gate 3W/L
• 5-Tap 2P/4P transmitter Total gate 15W/L

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5-Tap 2P/4P Shared Transmitter
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Receive Equalizer
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Dual Loop PLL/DLL Design

• Self-biased 4x or 5x RefClk Multiplier based on
  Maneatis, Sidiropoulos, Horowitz
• CDR is DLL w/PLL vectors phase mixers
• 2X oversampling per bit (edge data)
• Dual loop design avoids harmonic locking

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Multi PAM clock recovery

• Data can transition from and to any level
• 2PAM CDR may lock to any of three strong timing
  distributions

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4-PAM Edges CDR
Major

• Timing errors possible if using a 2-PAM CDR on
  unrestricted 4-PAM data

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2-PAM/4-PAM CDR

• 2-PAM mode - uses major transitions
• 4-PAM mode - uses minor transitions

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Complete Link Block Diagram
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Agenda

• The Backplane Environment
• PAM2 vs. PAM4 signaling
• Link Design
• Simulation Measured Results
• Conclusions

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Measured PLL (TX) Jitter
2.3psec rms 18psec p-p _at_ 3.2GHz (6.4Gbps _at_ 2P,
12.8Gbps _at_ 4P)

• Includes on-chip noise

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Measured 4-PAM CDR Performance

• 2-PAM CDR on 4-PAM data
• 60ps p-p _at_ 8Gb/s

• 4-PAM CDR uses only minor transitions
• Lower dither jitter
• 35ps p-p _at_ 8Gb/s

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System Level Simulink Model
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(No Transcript)
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TX Equalization Effectiveness
No EQ
w/TX EQ
Un-folded 10T
Folded
20 of FR4 two connectors
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2-PAM eye with no equalization at 6.4Gb/s over
20 BP
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2-PAM eye with Tx equalization at 6.4Gb/s over
20 BP
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10G Eyes System Margin Shmoos

• 3/20/3 26 Trace 2 Connectors
• Tested to BER lt 10-15

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(left) 4-PAM PDF showing broad distributions and
(right) eye including worst-case transitions at
10Gb/s over a 20 backplane.
Data Level Distribution With No Receive
Equalization
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Data Level Distribution With Receive Equalization
(left) 4-PAM PDF showing narrowed distributions
and (right) eye including worst-case transitions
showing improvement of both distributions and
eyes. 10Gb/s over 20 BP
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RX Equalization Effectiveness

• Measured system margin with device shmoo shows
  large improvement with RX Eq
• 20 of FR4 two
  connectors

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Agenda

• The Backplane Environment
• PAM2 (NRZ) vs. PAM4 signaling
• Link Design
• Simulation Measured Results
• Conclusions

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Prototype System Evaluation

• Constructed line cards with commercially
  available and next generation connectors
• A complete matrix of backplanes was constructed
• 5 connectors X 3 materials
• Counterbored/Non-Counterbored vias
• System components (packages, vias, connectors,
  traces, etc.) were individually measured to
  construct complete channel models

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2P/4P Performance by Configuration

• Configuration Space
• 5 Different connectors
• 2 Different dielectrics
• 2 Different via types
• 2 Different Trace lengths
• Top Bottom Layers

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Summary Conclusions

• Backplane Environment is very challenging
• Frequency dependent dielectric and skin loss
• Many variations between channels
• Reflection locations in time vary with length and
  Nyquist
• Does not scale due to increasing need for
  complexity
• With the right silicon approaches copper
  backplanes can run at 10Gb/s