Design and Implementation of Turbo Decoders for Software Defined Radio

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Design and Implementation of Turbo Decoders for
Software Defined Radio

• Yuan Lin1, Scott Mahlke1, Trevor Mudge1, Chaitali
  Chakrabarti2, Alastair Reid3, Krisztian Flautner3
• 1Advanced Computer Architecture Lab, University
  of Michigan
• 2Department of Electrical Engineering, Arizona
  State University
• 3ARM, Ltd.

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Advantages of Software Defined Radio

• Multi-mode operations
• Lower costs
• Faster time to market
• Prototyping and bug fixes
• Chip volumes
• Longevity of platforms
• Protocol complexity favors software dominated
  solutions
• Enables future wireless communication innovations
• Cognitive radio

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SDR Design Objectives for W-CDMA

• Programmable processor
• Same hardware should support Turbo decoder as
  well as other DSP algorithms
• Throughput requirements
• 2Mbps
• Power constraints
• 100mW 500mW

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SODA DSP Processor for SDR
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SODA PE SIMD Pipeline
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SODA PE SIMD Shuffle Network
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SODA PE Scalar Pipeline
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Turbo Decoder on SODA

• Most computationally intensive algorithm in
  W-CDMA
• Hardest algorithm to parallelize
• Implementation outline
• MaxLogMAP trellis computation with SIMD
  operations
• Parallelizing trellis computations through
  sliding window
• Interleaver implementation

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Trellis Computation on SODA

• Two types of trellis diagram configurations
• Blue edges (0-branch), Red edges (1-branch)
• Mapping trellis of size S onto SODA of SIMD size
  T

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Forward Trellis on SODA (S T)
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Handling SIMD Misalignment
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Sliding Window on SODA

• Problem
• W-CDMA uses K4, 8 wide trellis
• SODA has 32-wide SIMD
• Solution
• parallelize trellis computation by implementing
  sliding window
• fully utilize SIMD width
• achieving higher-throughput in the process

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Sliding Window Parallelization
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Sliding Window on SODA (S lt T)
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Turbo Decoder System Operations
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SODA DMA Modifications

• Traditional DMA controller
• Designed for block data transfer
• 1 source and 1 destination address per block
• Modified DMA controller
• Adding data interleaving functionality to DMA
• Needs to handle scalar data transfers
• 1 source and 1 destination address per scalar

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Achieved Performance on SODA

• SODA operates at 400MHz
• Can achieve 2.08Mbps with I 5

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Conclusion Future Work

• Implementation summary
• SODA consumes lt100mW in 90nm
• Meets W-CDMA throughput requirements
• Hardware features
• wide SIMD execution
• SIMD permutation network
• smart DMA
• Beyond 3G
• Support for higher throughput 3G protocols
• Multi-processor SODA for Turbo decoder
• LDPC decoding

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Questions?

• www.eecs.umich.edu/sdrg