4 Bit Arithmetic Logic Unit

1
4 Bit Arithmetic Logic Unit

• Presented by
• Ipsita Praharaj,
• Shalaka Ghawate
• Advisor Dr. David Parent
• Date05/11/04

2
Agenda

• Abstract
• Introduction
• - why
• - Simple Theory
• - Background
• Summary of results
• Project Details
• Cost Analysis
• Conclusions

3
Abstract

• Goal is to design a 4-bit ALU driving upto 30fF
  that can perform the following operations
• -FULL ADDER
• -AND
• -OR
• -NOR

4
Introduction

• ALU is a building block of several circuits.
• Understanding how an ALU is designed and how it
  works is essential to building any advanced logic
  circuits.
• Using this knowledge and experience, we can move
  on to designing more complex integrated circuits.
• Design consists of different kind of logicRipple
  carry adder, full adder, AND, OR, NOR, DFF, MUX.

5
Block diagram of 4 bit ALU
6
Project Details

• -There are total of 19 pin outs in our design.
• including VDD and GND.
• -There are 9 D flip-flops at the input and 4 at
  the output.
• -There is a 41 MUX to select the output.
• -Create schematics and layouts for adder, AND,
  OR, MUX, in the cadence tool.
• -Test the schematic using test bench.
• -Create schematic and layout for 1 bit ALU now
  using the schematics for the basic logical units.
  
• -Test the schematic for 1 bit ALU.
• -Create the single bit ALU to create a 4 bit ALU
  layout.
• -Run DRC extracted and LVS check to verify the
  design.

7
DFF

• DFF are placed on either side of the
  combinational logic.
• Hold time 0.586n(Fall)
• 0.515n(Rise)
• Setup time0.521n(Fall)
• 0.450n(Rise)

8
Long path calculations
9
Full Adder Schematic
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Full Adder Layout
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Full Adder LVS Report
12
2-to-1 MUX schematic
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4-to-1 MUX layout
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4-bit ALU schematic
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4-bit ALU layout
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4 bit ALU(LVS Report)
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DFF schematic
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DFF layout
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DFF LVS report
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4 bit ALU with DFF schematic
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4 bit ALU with DFF layout
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4 bit ALU with DFF LVS report
23
Transient Analysis
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Worst case (Tphl)
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Worst case (Tplh)
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Post extraction simulation
27
Results

• The ALU performs all 4 functions at a 200Mhz
  clock and a load of 30fF.
• We meet the power specifications.
• Area of the our layout192micron375micron.

28
Cost Analysis

• Time spent on each phase of the project.
• - Logic design 1 week.
• - Logic check 1 week
• -Individual schematic 5 days
• - Integration of schematic blocks 1 week
• - Layouts 2 weeks
• - Post extraction check 2 days

29
Acknowledgements

• Thanks to Cadence Design systems for the VLSI
  labs
• Thanks to Professor David Parent for his guidance.