Advanced Implantation Detector Array (AIDA):

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Advanced Implantation Detector Array
(AIDA) Update Issues
presented by Tom Davinson on behalf of the AIDA
collaboration (Edinburgh Liverpool STFC DL
RAL)
Tom Davinson School of Physics The University of
Edinburgh
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DESPEC Implantation DSSD Concept

• SuperFRS, Low Energy Branch (LEB)
• Exotic nuclei energies 50 200MeV/u
• Implanted into multi-plane, highly segmented
  DSSD array
• Implant decay correlations
• Multi-GeV DSSD implantation events
• Observe subsequent p, 2p, a, b, g, bp, bn
  decays
• Measure half lives, branching ratios, decay
  energies
• Tag interesting events for gamma and neutron
  detector arrays

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Implantation DSSD Configurations

• Two configurations proposed
• 8cm x 24cm
• cocktail mode
• many isotopes measured simultaneously
• b) 8cm x 8cm
• high efficiency mode
• concentrate on particular isotope(s)

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AIDA DSSD Array Design
courtesy B.Rubio

• 8cm x 8cm DSSDs
• common wafer design for 8cm x 24cm and 8cm x 8cm
  configurations
• 8cm x 24cm
• 3 adjacent wafers horizontal strips series
  bonded
• 128 pn junction strips, 128 nn ohmic strips
  per wafer
• strip pitch 625mm
• wafer thickness 1mm
• DE, Veto and up to 6 intermediate planes
• 4096 channels (8cm x 24cm)
• overall package sizes (silicon, PCB, connectors,
  enclosure )
• 10cm x 26cm x 4cm or 10cm x 10cm x 4cm

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ASIC Design Requirements
Selectable gain 20 1000 20000 MeV FSR Low
noise 12 600 50000 keV FWHM energy
measurement of implantation and decay
events Selectable threshold lt 0.25 10
FSR observe and measure low energy b, b
detection efficiency Integral non-linearity lt
0.1 and differential non-linearity lt 2 for gt
95 FSR spectrum analysis, calibration,
threshold determination Autonomous overload
detection recovery ms observe and measure
fast implantation decay correlations Nominal
signal processing time lt 10ms observe and
measure fast decay decay correlations Receive
(transmit) timestamp data correlate events with
data from other detector systems Timing trigger
for coincidences with other detector systems DAQ
rate management, neutron ToF
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Schematic of Prototype ASIC Functionality

• Note prototype ASIC will also evaluate use of
  digital signal processing
• Potential advantages
• decay decay correlations to 200ns
• pulse shape analysis
• ballistic deficit correction

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Design Study Conclusions

• 4 or 6 Si wafer technology?
• - integrated polysilicon bias resistors (15MW)
• - separate coupling capacitors (require
  22nF/200V)
• Radiation damage mitigation measures essential
• - detector cooling required
• Noise specification (12keV FWHM) not
  unreasonable
• Discriminator
• - low threshold (lt50keV) slow, compromised for
  ID gt 100nA
• - separate timing discriminator higher
  threshold
• x1000 overload recovery ms achievable
• - depends on input pulse shape
• - optimisation requires more information

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AIDA Design Concept
Detail of DSSSD detector layers and detector
enclosure
Beam
courtesy Dave Seddon Rob Page, University of
Liverpool
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AIDA Current Status

• Edinburgh Liverpool CCLRC DL CCLRC RAL
  collaboration
• - 4 year grant period
• - DSSD design, prototype and production
• - ASIC design, prototype and production
• - Integrated Front End FEE PCB development and
  production
• - Systems integration
• - Software development
• Deliverable fully operational DSSD array to
  DESPEC
• Proposal approved fully funded - project
  commenced August 2006
• Detailed specification published November 2007
• Technical Specification release to project
  engineers January 2007
• Detailed ASIC design engineering underway

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AIDA Resources Tasks

• Cost
• Total announced value proposal 1.96M
• Support Manpower
• CCLRC DL c. 4.2 SY FEE PCB Design
• DAQ h/w s/w
• CCLRC RAL c. 3.5 SY ASIC Design simulation
• ASIC Production
• Edinburgh/Liverpool c. 4.5 SY DSSD Design
  production
• FEE PCB production
• Mechanical housing/support
• Platform grant support CCLRC DL/Edinburgh/Liverp
  ool

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AIDA Current Status

• DSSD request for tender
• Prototype ASIC design submission 2008/Q1
• FEE design underway
• liquid cooling required (cf. AGATA digitiser
  module)
• Evaluating
• 10nF/100V capacitor arrays
• Analog Devices AD9252 14-bit/50MSPS ADC
• DSSD response high energy heavy-ions
• simulations Luigi Bardelli et al.
• Texas AM (40MeV/u) November 2008
• GSI (100MeV/u) March 2009

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Outstanding Issues approaching the Rubicon

• Package size
• 10cm x 26cm x 4cm (10cm x 10cm x 4cm)
• Mechanical design concepts
• 10cm x 26cm AIDA/ToF/Ge
• 10cm x 26cm AIDA/4p Neutron Detector
• 10cm x 10cm AIDA/TAS
• others?
• Review ASIC Project Specification
• DESPEC project requirements satisfied?

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AIDA/ToF/Ge
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AIDA/4p Neutron (NERO)
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AIDA/TAS
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AIDA Project Information
Project web site http//www.ph.ed.ac.uk/td/AIDA/
welcome.html Design Documents http//www.ph.ed.a
c.uk/td/AIDA/Design/design.html Project
Technical Specification ASIC Project
Specification v1.3 FEE Specification v0.5 The
University of Edinburgh (lead RO) Phil Woods et
al. The University of Liverpool Rob Page et
al. STFC DL RAL John Simpson et al. Project
Manager Tom Davinson
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Acknowledgements
This presentation includes material from other
people Thanks to Ian Lazarus Patrick
Coleman-Smith (STFC DL) Steve Thomas (STFC
RAL) Dave Seddon Rob Page (University of
Liverpool) Berta Rubio (IFIC, CSIC University of
Valencia)
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Implantation Decay Correlation

• DSSD strips identify where (x,y) and when (t0)
  ions implanted
• Correlate with upstream detectors to identify
  implanted ion type
• Correlate with subsequent decay(s) at same
  position (x,y) at times t1(,t2, )
• Observation of a series of correlations enables
  determination of energy
• distribution and half-life of radioactive decay
• Require average time between implants at
  position (x,y) gtgt decay half-life
• depends on DSSD segmentation and implantation
  rate/profile
• Implantation profile
• sx sy 2cm, sz 1mm
• Implantation rate (8cm x 24cm) 10kHz, kHz
  per isotope (say)
• Longest half life to be observed seconds

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AIDA General Arrangement
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Representative ASIC Noise Analysis
Note amongst other assumptions, we assume
detector cooling

• Minimise ballistic deficit
• shaping time gt10x tr
• operate with t ms
• noise dominated by leakage current for ID gt 10 nA

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AIDA Workplan
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Diagram (above) of the FEE boards as they would
fit in the vertical plane. The grey rectangles
are heat conductive foam pads which conform to
the component outlines and conduct the heat to
the water cooled metalwork. The green is pcb, the
orange is a Samtec 80 pin connector with a 2.3mm
height and the dark brown is the ASIC. The
connections to the detector will be on the
mezzanine boards to the left and to the
acquisition network computers and BUTIS on the
right. These are not shown. Diagram ( alongside)
shows the layout of a sub-board.