CMOS VLSI Design Lecture 0: Introduction

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CMOS VLSIDesignLecture 0 Introduction

• (Material adapted from Harris lecture notes)

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Outline

• Syllabus
• Logistics (time, place, instructor, website,
  textbook)
• Grading
• Topics
• Outcomes
• Introduction to VLSI
• A brief history
• MOS transistors
• CMOS logic gates

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Course Information (1)

• Time and Place
• Tue/Thu 545-700pm, ENGR 1.250
• Instructor
• Weidong Kuang
• kuangw_at_panam.edu
• ENGR 3.270, 316-7133
• Office hours walk in most mornings
• Course Web Page
• http//www.engr.panam.edu/kuangw/courses

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Course Information (2)

• Prerequisites
• Digital logic (ELEE2330) and Solid state devices
  (ELEE 4328), or equivalent
• I assume you know the following topics
• Boolean algebra, logic gates, etc.
• Undergraduate physics Ohms law, resistors,
  capacitors, etc.
• Undergraduate math calculus

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Course Information (3)

• Textbook
• Weste and Harris. CMOS VLSI Design(3rd edition)
• Addison Wesley
• ISBN 0-321-14901-7

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Course Information (4)

• Grading
• 50 project
• 10 homework
• 10 mid-term exam
• 30 final exam

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Course Information (5)

• Topics
• CMOS logic gate
• CMOS fabrication and layout
• MOS transistor modeling
• Performance analysis for VLSI circuits
• Combinational circuits
• Sequential circuits
• Memory circuits
• Low power design
• Testing
• System on chip

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Course Information (6)

• Outcomes
• Use the Cadence CAD tool to design a chip
  including (depending on tool availability)
• Schematic entry
• Layout
• Transistor-level cell design
• Gate-level logic design
• Hierarchical design
• Switch-level simulation
• Design rule checking

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Course Information (7)

• Outcomes
• Estimate and optimize combinational circuit delay
  using RC delay models and logical effort
• Design high speed and low power logic circuits
• Understand interconnect and reliability issues
• Design functional units including adders,
  multipliers, ROMs, SRAMs, and PLAs
• Beware of the VLSI trends and challenges

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Introduction

• Integrated circuits many transistors on one
  chip.
• Very Large Scale Integration (VLSI) very many
• Complementary Metal Oxide Semiconductor
• Fast, cheap, low power transistors
• Today How to build your own simple CMOS chip
• CMOS transistors
• Building logic gates from transistors
• Transistor layout and fabrication
• Rest of the course How to build a good CMOS chip

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A Brief History

• 1958 First integrated circuit
• Flip-flop using two transistors
• Built by Jack Kilby at Texas Instruments
• 2003
• Intel Pentium 4 mprocessor (55 million
  transistors)
• 512 Mbit DRAM (gt 0.5 billion transistors)
• 53 compound annual growth rate over 45 years
• No other technology has grown so fast so long
• Driven by miniaturization of transistors
• Smaller is cheaper, faster, lower in power!
• Revolutionary effects on society

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Annual Sales

• 1018 transistors manufactured in 2003
• 100 million for every human on the planet

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Invention of the Transistor

• Vacuum tubes ruled in first half of 20th century
  Large, expensive, power-hungry, unreliable
• 1947 first point contact transistor at Bell Labs
• John Bardeen and Walter Brattain at Bell Labs
• Read Crystal Fire
• by Riordan, Hoddeson

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Transistor Types

• Bipolar transistors
• npn or pnp silicon structure
• Small current into very thin base layer controls
  large currents between emitter and collector
• Base currents limit integration density
• Metal Oxide Semiconductor Field Effect
  Transistors
• nMOS and pMOS MOSFETS
• Voltage applied to insulated gate controls
  current between source and drain
• Low power allows very high integration
• Simpler fabrication process

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MOS Integrated Circuits

• 1970s processes usually had only nMOS
  transistors
• Inexpensive, but consume power while idle
• 1980s-present CMOS processes for low idle power

Intel 1101 256-bit SRAM
Intel 4004 4-bit mProc
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Moores Law

• 1965 Gordon Moore plotted the number of
  transistors on each chip
• Fit straight line on semilog scale
• Transistor counts have doubled every 26 months

Integration Levels SSI 10 gates MSI 1000
gates LSI 10,000 gates VLSI gt 10k gates
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Corollaries

• Many other factors grow exponentially
• Ex clock frequency, processor performance

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Scaling Down a Mystery

• In 1971, minimum dimensions of 10 um in 4004.
• In 2003, minimum dimensions of 130 ns in
  Pentium4.
• Scaling down forever ? (No, transistors cannot
  be less than atoms)
• Many predictions of fundamental limits to scaling
  have already proven wrong
• We believe that scaling will continue for at
  least another decade.
• What is the future?

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Periodic Table
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Silicon Lattice

• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four neighbors

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Dopants

• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts
  poorly
• Adding dopants increases the conductivity
• Group V (Arsenic) extra electron (n-type)
• Group III (Boron) missing electron, called hole
  (p-type)

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p-n Junctions

• A junction between p-type and n-type
  semiconductor forms a diode.
• Current flows only in one direction

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nMOS Transistor

• Four terminals gate, source, drain, body
• Gate oxide body stack looks like a capacitor
• Gate and body are conductors
• SiO2 (oxide) is a very good insulator
• Called metal oxide semiconductor (MOS)
  capacitor
• Even though gate is
• no longer made of metal

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nMOS Operation

• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF

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nMOS Operation Cont.

• When the gate is at a high voltage
• Positive charge on gate of MOS capacitor
• Negative charge attracted to body
• Inverts a channel under gate to n-type
• Now current can flow through n-type silicon from
  source through channel to drain, transistor is ON

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pMOS Transistor

• Similar, but doping and voltages reversed
• Body tied to high voltage (VDD)
• Gate low transistor ON
• Gate high transistor OFF
• Bubble indicates inverted behavior

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Power Supply Voltage

• GND 0 V
• In 1980s, VDD 5V
• VDD has decreased in modern processes
• High VDD would damage modern tiny transistors
• Lower VDD saves power
• VDD 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

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Transistors as Switches

• We can view MOS transistors as electrically
  controlled switches
• Voltage at gate controls path from source to drain

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CMOS Inverter
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CMOS Inverter
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CMOS Inverter
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NAND Gate
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CMOS NOR Gate
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3-input NAND Gate

• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

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3-input NAND Gate

• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

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CMOS Gate Design

• Activity
• Sketch a 4-input CMOS NOR gate

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Complementary CMOS

• Complementary CMOS logic gates
• nMOS pull-down network
• pMOS pull-up network
• a.k.a. static CMOS

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Series and Parallel

• nMOS 1 ON
• pMOS 0 ON
• Series both must be ON
• Parallel either can be ON

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Conduction Complement

• Complementary CMOS gates always produce 0 or 1
• Ex NAND gate
• Series nMOS Y0 when both inputs are 1
• Thus Y1 when either input is 0
• Requires parallel pMOS
• Rule of Conduction Complements
• Pull-up network is complement of pull-down
• Parallel -gt series, series -gt parallel

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Compound Gates

• Compound gates can do any inverting function
• Ex

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Example O3AI

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Signal Strength

• Strength of signal
• How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• nMOS pass strong 0
• But degraded or weak 1
• pMOS pass strong 1
• But degraded or weak 0
• Thus nMOS are best for pull-down network

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Pass Transistors

• Transistors can be used as switches

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Transmission Gates

• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well

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Tristates

• Tristate buffer produces Z when not enabled

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Nonrestoring Tristate

• Transmission gate acts as tristate buffer
• Only two transistors
• But nonrestoring
• Noise on A is passed on to Y

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Tristate Inverter

• Tristate inverter produces restored output
• Violates conduction complement rule
• Because we want a Z output

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Multiplexers

• 21 multiplexer chooses between two inputs

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Gate-Level Mux Design

• How many transistors are needed? 20

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Transmission Gate Mux

• Nonrestoring mux uses two transmission gates
• Only 4 transistors

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Inverting Mux

• Inverting multiplexer
• Use compound AOI22
• Or pair of tristate inverters
• Essentially the same thing
• Noninverting multiplexer adds an inverter

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41 Multiplexer

• 41 mux chooses one of 4 inputs using two selects
• Two levels of 21 muxes
• Or four tristates

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D Latch

• When CLK 1, latch is transparent
• D flows through to Q like a buffer
• When CLK 0, the latch is opaque
• Q holds its old value independent of D
• a.k.a. transparent latch or level-sensitive latch

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D Latch Design

• Multiplexer chooses D or old Q

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D Latch Operation
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D Flip-flop

• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop,
  master-slave flip-flop

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D Flip-flop Design

• Built from master and slave D latches

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D Flip-flop Operation
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Race Condition

• Back-to-back flops can malfunction from clock
  skew
• Second flip-flop fires late
• Sees first flip-flop change and captures its
  result
• Called hold-time failure or race condition

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Nonoverlapping Clocks

• Nonoverlapping clocks can prevent races
• As long as nonoverlap exceeds clock skew
• We will use them in this class for safe design
• Industry manages skew more carefully instead