Xilinx OnChip Debug

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Xilinx On-Chip Debug
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Debug and Verification is Critical
Final Device

• Debug and verification can account for over 40
  of an FPGA design time
• Serial nature of debug and verification can make
  it difficult to optimize
• Inefficient strategy may result in product launch
  delay
• Loss in market share
• Loss of first-to-market advantages

Design Verification and Debug
40 of Design Time
Design Implementation
Design Specification
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Traditional Debug Challenges

• Limited Internal Visibility
• How do I access the embedded system bus
• Hard IP Cores
• Cant get internal access to
• Full Scan Insertion
• Increases overhead
• Its Too Late Anyway!
• Re-spins are ENORMOUSLY expensive
• Co-Verification
• Tools are cumbersome and slow
• Modeling issues

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Built For Debug - the Platform FPGA

• FPGA Enables Full Internal Visibility
• ChipScope Pro tools provide complete on-chip
  access
• Access Processor System Busses
• ChipScope Pro Integrated Bus Analyzer
• Flexible On-Chip Debug
• Small, efficient cores access any node or signal
  and can be removed at any time
• Its Never Too Late in an FPGA!
• Fix problems during development AND after product
  deployment
• Enable Complete System Verification
• Debug systems in real-time
• No need to extrapolate behavior

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Traditional Logic Analysis Method Dedicated pins
connected to logic analyzer
External Logic Analyzer
Pins
Probe points

• Requires Extensive Dedicated I/O for Debug
• Driving signals to external I/O introduces
  additional problems
• Inflexible solution
• Difficult or impossible to add additional debug
  pins if needed
• Limited visibility to on-chip activity

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ChipScope Pro On-Chip Debug Integrated Logic
Analyzer Core
ChipScope Pro
JTAG

• No I/O pins required for debug
• Access via the JTAG Port
• On-Chip access to every signal and node in the
  FPGA design
• Driving signals to external I/O introduces
  additional problems
• Add and remove cores at any time in the design
  process

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ChipScope Pro On-Chip Debug Integrated Bus
Analyzer Core
ChipScope Pro
Virtex-II Pro
XC2VP20 FF1152

• No I/O pins required for debug
• Access via the JTAG Port
• On-Chip System Bus Analysis
• ChipScope Pro Integrated Bus Analysis of the
  CoreConnect On-Chip Peripheral bus (OPB)
• Includes transaction debug and protocol violation
  detection

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Choose the Core that Best Meets Your Design
Requirements

• Virtual Input Output Core (VIO)
• Virtual Inputs and Outputs
• Stimulate logic with pulse trains

• Integrated Logic Analysis
• Core (ILA)
• Access internal nodes and signals
• Debug and verify signal behavior
• Define detailed trigger conditions

User Logic
Aurora

• Integrated Bus Analysis
• Core (IBA)
• PLB and OPB specific Bus analysis cores
• Protocol detection
• Debug and verify control, address, and data buses

OPB GPIO
Bridge
OPB Bus
PLB Bus
Arbiter

• Agilent Trace Core 2 (ATC2)
• Agilent created core enabling On-chip debug of
  Xilinx FPGAs usingAgilent FPGA Dynamic Probing

OPB SDRAM
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Debug Logic Anywhere Within the FPGA
Memory Controller
Clock
Data
ILA
Clock
Trigger Out
Trigger 0
Trigger 1
Trigger 2
Trigger 3
Address

• Identify logic that you need to debug and verify
• ChipScope Pro cores are placed directly within
  the logic and
• Function as virtual test headers
• Provide access any signal or node with the FPGA
• Debug at the system clock rate

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ChipScope Pro Tools Allow You to Add Cores at
Any Time in the Design

• ChipScope Pro Core Generator
• Generate and add cores at the beginning of the
  design process
• ChipScope Pro Core Inserter
• Target existing signals and generate and insert
  cores into a synthesized design
• ChipScope Pro configuration
• Simplify iterative debug and verification process

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ChipScope Pro Interface Makes FPGA Debug Easy
ChipScope Pro Analyzer functions as a
logic analyzer, bus analyzer, and control console

• Access ChipScope cores via JTAG or user defined
  Trace port
• Configure FPGA, define trigger conditions, and
  view data via ChipScope Pro analyzer running on
  a PC

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Remote Debug and Verification
ChipScope Pro Analyzer server connected to
fielded system enabled for remote debug and
verification
Debug remote systems from your office via
ChipScope Pro Analyzer client
ChipScope Pro Analyzer server connected to Xilinx
development board enabled for remote debug and
verification
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Exclusive Capability Combines On-Chip Debug with
External Logic Analysis

• Measures new groups of internal FPGAsignals in
  seconds without
• Recompiling the design
• Impacting the timing of the design
• Save 15 min to 10 hours per new measurement
• Achieves wider internal visibility over a fixed
  number of pins
• 64 internal probe points for every pin conserves
  FPGA resources
• Save 8 hours per problem by not having to create
  a testbench
• Eliminates error prone time consuming tasks
• Automates signal/bus labeling from FPGA design to
  logic analyzer
• Automatically maps FPGA pins from board layout to
  logic analysis channels
• Save 2 to 30 minutes per new measurement

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Compatibility

• Agilent Logic Analyzers
• 1680-series
• 1690-series
• 16900-series with following modules
• 16740 series
• 16750 series
• 16910 series
• 16950 series

• Xilinx FPGAs
• Virtex-4
• Virtex-II Pro
• Virtex-II
• Spartan-3E
• Spartan-3

Core insertion/distribution ChipScope Pro ISE
design software
Probing Soft touch, mictor, samtec, flying lead,
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Xilinx ChipScope ProEnabling Complete FPGA Debug
Solutions
IBA (EDK Integration)
FPGA Dynamic Probing
System Complexity
ILA, VIO
ILA, VIO
Debug and Verification Resources (Deep Storage,
Complex Triggers)
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Whats Next

• View the ChipScope Pro product demo online
• Learn how to insert ChipScope Pro cores into a
  design
• Learn how to use the ChipScope Pro analyzer to
  debug and verify

• ChipScope Pro for the engineering curriculum
• Donations available to Professors
• www.xilinx.com/univ