Towards Electronics for a Long Baseline Neutrino Detector - PowerPoint PPT Presentation

1 / 21
About This Presentation
Title:

Towards Electronics for a Long Baseline Neutrino Detector

Description:

Solutions have been adapted from existing ASICS. driven by cost, timescale, physics. ... developed around different existing ASICs. heavy use of FPGAs. huge ... – PowerPoint PPT presentation

Number of Views:12
Avg rating:3.0/5.0
Slides: 22
Provided by: alfons91
Category:

less

Transcript and Presenter's Notes

Title: Towards Electronics for a Long Baseline Neutrino Detector


1
Towards Electronics for a Long Baseline
Neutrino Detector
?
  • Alfons Weber
  • STFC University of Oxford

2
Issues
  • Introduction
  • State of the Art
  • MINOS/OPERA
  • NOVA
  • T2K/MINERVA
  • Requirements
  • physics
  • photo detectors
  • RD needs

3
Introduction
  • There are N Detectors
  • At least 2N different electronics have been used
    to read them out
  • No unique solution
  • Solutions have been adapted from existing ASICS
  • driven by cost, timescale, physics.
  • not ideal
  • But get the job done

4
Tensions
  • Near Detectors
  • high rate
  • beam synchronisation
  • limited channel count
  • Far Detectors
  • low rate
  • no beam signal available
  • huge channel count
  • Performance
  • high dynamic range, precise timestamps
  • 100 lifetime
  • low cost

5
What the following is about
  • Electronics, need to integrate with
  • DAQ
  • photo detectors
  • Photo-detectors
  • PMT, APD, MPPC
  • DAQ
  • PCs?
  • Detector
  • scintillator with WLS fibre
  • large PMT arrays?

6
Solution MINOS ND
Input current
8-bit FADC value
Analog Voltage
QIE
FADC
FIFO
3 bit range code 2 bit CAP-ID code
CAP-ID QIE has 4 copies of current
divider/integrator ? 4 capacitor IDs
Every channel in the detector (9240) produces,
every 18.87 nsec FADC, RANGE, CAP-ID 1.4fC
lowest count sensitivity, 16-bit effective
dynamic range
QIE output voltage
Input charge
  • Based on existing QIE ASIC
  • dead-timeless for up to 20 µsec (spill)

7
Solution MINOS ND (II)
Timing System
8 MASTER crates
44 MINDER crates
Front End (MINDER/MENUS)
Readout (MASTER)
Data Acquisition
Analogue PMT Pulse
Fast readout of digital data in response to
trigger
PVIC Transfers to PCs
8
Solution MINOS FD/OPERA
  • MINOS developed an ASIC chip for PMT readout with
    IDEAS
  • 32 channels VA32_HDR11
  • shaping
  • amplification
  • sample hold
  • output driver to ADC
  • Excellent product
  • fast shaping 500 nsec
  • noise lt 2 fC
  • lineargt 20 pC
  • 6 ASICs multiplexed onto 1 ADC

9
Solution MINOS FD (system)
  • Timing System
  • Absolute time from GPS(?tabs 200 nsec)
  • optical distribute along large detector (?trel
    4 nsec)
  • Trigger-less DAQ system
  • ASIC close to PMT
  • ADC in VME crate
  • fast PVIC-bus to PC trigger farm
  • search for hits correlated in space and time

10
Solution T2K/280m MINERVA
Spill Structure
2-3.53s
2-3.53s
Bunch Structure
Chip Time Structure
integration
reset
  • 8 (15) batches
  • Separated by 540 (241) nsec
  • charge integrated in batches

11
TRIP-t Front-end architecture
preamp
gain adjust 1,2,3,8
very simplified neglecting features not
relevant to ND280 operation
integrate/reset
Qin
analogue pipeline
1pF
3pF
discriminator
x10
gain 1 or 4
disc. O/P
Vth
reset
  • only preamp gain affects signal feeding
    discriminator
  • no fine control (x1 or x4)
  • discriminator threshold Vth
  • common to all channels on chip
  • analogue bias settings
  • gain, Vth, etc.
  • programmable via serial interface

12
Solution T2K (System Overview)
SiPM0
SiPM63
SiPM0
SiPM63
SiPM0
SiPM63



TFB0
TFB1
TFB47

TPS
Trigger Primitives
Power distribution
Clk trg
data
RMM0
CTM
Cosmic trigger
Gigabit/Ethernet
Clk trg
Clk trg
AcronymsTFB TRIP-t front-end boardRMM r/o
merger moduleCTM global trigger
moduleMCM master clock moduleSCM slave clock
moduleTPS TRIP-t power supplyFPN front-end
proc. node (PC)
Gigabit/Ethernet
MCM
SCM
FPN
Clk trg
Special trigger
GPS 1Hz/100MHz
(Acc. RF)
Gigabit/Ethernet
Spill trig
Gigabit/Ethernet
13
(No Transcript)
14
(No Transcript)
15
Solution NOvA
16
Common Thread
  • Different solutions for near and far detectors
  • developed around different existing ASICs
  • heavy use of FPGAs
  • huge variation in cost
  • 20 - 300 per channel
  • DAQ and electronics cant be developed
    independently
  • later solutions move towards commercial back ends

17
Requirements
  • high QE photo detectors
  • bigger detectors ? cheaper
  • low noise electronics
  • low readout thresholds ? bigger detectors
  • dynamic range
  • limited? 11000
  • Timing
  • O(1nsec)
  • low trigger threshold
  • low and high rate environment

?
18
Requirements (II)
  • Will take a long time for community to settle on
  • detector
  • photo detector
  • requirements
  • Try to develop multi-purpose ASIC
  • test beam
  • near detector
  • external trigger, limited lifetime
  • far detector
  • cheap, scalable, 100 lifetime, self-triggering

19
Ingredients
  • ADC
  • 11000
  • TDC
  • 1 nsec
  • Trigger
  • local/global
  • clock distribution
  • cheap HV supply
  • 30-1000 V
  • monitoring
  • commercial interfaces

20
The Pass
  • Resume
  • Performance is not leading edge
  • Cost is main driving factor
  • multi purpose device
  • Work needed
  • requirements capture
  • design multi-purpose readout system
  • Electronics
  • DAQ
  • Develop ASIC
  • develop test system

21
Who and Where?
  • Who is driving this?
  • which community
  • physicists vs. electronics engineers
  • Where can the work be done?
  • major labs
  • Universities
  • Has to be user driven.
  • Many questions, few answers.
Write a Comment
User Comments (0)
About PowerShow.com