How to use the VHDL and schematic design entry tools.

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How to use the VHDL and schematic design entry
tools.
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ABSTRACT

• Demonstrates how to create a top-level schematic
  that contains instantiations of the modules, and
  describe how to wire together the modules, and
  determine the circuit behavior by computer
  simulation.

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Starting the Xilinxs Software

• For PC users, start Xilinx program from the Start
  menu by selecting the following path Start ?
  Programs ? Xilinx Foundation Series 2.1i ?
  Project Manager

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Creating New Project

• Select OK
• New Project dialog box comes out
• Give NameLab5 create the directory path
  a\lab5
• Select OK

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Creating a New Schematic

• Click on the third item named Schematic Editor in
  the first flow chart box.

Schematic Editor
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Schematic Editor Window
Symbol Toolbox
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Libraries

• Click on the Symbols Toolbox icon
• Click on Select Libraries

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Instantiating VHDL Modules

• Select FJKSRE from the SC Symbols Window.
• Place four FJKSREs in the schematic editor window
  by simply dragging from the SC Symbols Window.

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Instantiating VHDL Modules

• Similarly select AND2.
• Place three AND2s in the Schematic Editor Window.

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Instantiating VHDL Modules

• Place one inverter in the Schematic Editor
  Window.
• Select VCC and GND and place it on the Schematic
  Editor Window.

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Adding Hierarchy Connectors

• Click on the Hierarchy Connector Symbol.

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(No Transcript)
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Wiring the Components

• Go to the left toolbar and click on Draw wires
  Symbol.
• To make a connection
• Click once at the vertex of a pin
• Extend the wire to the desired length
• Click on the location you want the wire to
  terminate.

Draw Wires
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Simulation

• Click on the Simulator button in the taskbar on
  the top of the workspace.

Simulator
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Simulation

• Inside the Waveform Viewer Window click on Add
  Signals.

Double Click
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Setting the Field Values

• Click on the text that says Clock, then click on
  the Select Simulator button in the Waveform
  Viewer Window.

Select Simulators
Double Click
Click
Click
Click
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Setting the Field Values

• Click on the text that says Reset, then click the
  Logic States Button.

Simulation Step
Logic States
Click
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Final Output
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Reference

• Lab Manual