Bii v2 with ACE16k

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Wave Computer Implementations

• Bi-i v2 with ACE16k
• Bi-i 301F with FPGA
• Bi-i v2 with LOCUST sensor
• Bi-i v2 with Xenon V3 chip
• Bi-i v2 with Xenon V3 chip

• CACE
• Eye-RIS
• SCAMP 3
• Falcon
• Playstation with Cell multi-processor
• Cell multi-processor simulator

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Bi-i v2 with ACE16k
ACE 16k chip AnaFocus Seville, Spain
Bi-i system AnaLogic Computers Ltd. Budapest,
Hungary
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Bi-i 301F with FPGA

• Real time video analytics
• Multi-core processor
• Implemented in FPGA
• Over 50 processors
• Trades resolution to speed
• High resolution application
• Low power
• Low costs

Bi-i 301F with FPGA Eutecus, Inc. Berkeley,
California
4
Bi-i v2 with LOCUST sensor

• Bio mimicking looming senor for automotive
  application
• High dynamic range vision sensor
• Per pixel AD
• Per pixel embedded memory
• LGMD processor

Locusts looming sensor cell (LGMD)
Control Unit
Digital Processor
LGMD
CAN-Bridge
Power Management
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Bi-i v2 with Xenon V3 chip

• Focal-plane sensor-processor array
• 64x64 pixel array (scalable)
• Digital processors
• Bump bonding sensor interface
• Arithmetic and morphologic processors
• 16, 8, 1 bit/pixel
• 30 GOPS
• Under 20mW

Xenon V3 Eutecus, Inc. Berkeley, California
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CACE1k chip

• A 0.5 ?m CMOS, prototype visual microprocessor
  consisting of 1024 processing units arranged into
  a 3232 grid
• Each processing unit has
• Programmable 2nd order dynamics
• Local analog and digital memories
• Nearest neighbor intra-layer connections and one
  inter-layer connection
• Weighted independent input and bias

Traveling wave
Retina simulation
IMSE-CNM, Seville-Spain
7
Q-Eye chip

• 176 x 144 sensor-processor array
• Analog processor in each cell
• 3x3 morphologic processor in each cell
• Diffusion network
• 8 bits accuracy
• 50 GOPS
• 60mm2 die area in 0.18um CMOS technology
• lt300mW typical power consumption

Eye-RIS system
Q-Eye chip architecture
AnaFocus, Seville-Spain
8
SCAMP 3 chip

• 128x128 sensor processor array
• Analog processors
• Addition, subtraction, scaling, logic
• 111 transistors/cell
• 49.35 ?m x 49.35 ?m
• 0.35 ?m technology, 1P3M
• 1.25 MHz clock
• 12 ?W (max.)
• 512 MIPS/mm2
• 104 GIPS/W

SCAMP3 chip
SCAMP3 evaluation system
University of Manchester, UK
9
Falcon

• Single and multi-layer CNN emulation in FPGA
• MTA-SZTAKI, Budapest
• Pázmány Péter Catholic University, Budapest

Configurable parameters Independent state,
template and constant width between 2 to 64
bits Number of templates Size of the
templates Width of the cell array slice Number of
layers Number and arrangement of the processor
cores
10
Playstation with Cell multi-processor

• Sony
• IBM
• Toshiba

• Multiprocessor on a chip
• 241M transistors, 235mm2
• 200 GFlops (SP) _at_3.2GHz
• 200 GB/s bus (internal) _at_ 3.2GHz
• Power Processor Element (PPE)
• general purpose
• running full-fledged OSs
• Synergistic Processor Element (SPE)
• optimized for compute density

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Cell multi-processor simulator

• Sony
• IBM
• Toshiba

• Heterogeneous, multi-core engine
• 1 multi-threaded power processor
• up to 8 compute-intensive-ISA engines
• Local Memories
• fast access to 256KB local memories
• globally coherent DMA to transfer data
• Pervasive SIMD
• PPE has VMX
• SPEs are SIMD-only engines
• High bandwidth
• fast internal bus (200GB/s)
• dual XDRTM controller (25.6GB/s)
• two configurable interfaces (76.8GB/s)
• numbers based on 3.2GHz clock rate

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Cell Blade

• Sony
• IBM
• Toshiba

• Cell BE Processor Blade (500GFLOPS peak)
• Dual 3.2GHz Cell BE Processor Configuration
• 1GB XDRAM (512MB per processor)
• Blade-mounted 40GB IDE HDD
• Dual Gigabit Ethernet (GbE) controllers
• Double-wide blade (uses 2 BladeCenter slots)
• Infiniband (IB) Option
• Qty 0-2 IB 4x Host Channel Adapters
• BC Chassis Configuration (3.5TFLOPS peak)
• Standard IBM BladeCenter One
• Max. 7 Blades per chassis (QS20 - 2 slots each)
• 2 Gigabit Ethernet switches
• External IB switches required for IB option