RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card

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RiceNIC A Reconfigurable and Programmable
Gigabit Network Interface Card
Jeff Shafer, Dr. Scott RixnerRice Computer
Architecture http//www.cs.rice.edu/CS/Architectu
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Networks are Essential!
NIC Features
Performance

• Software Programmability
• Dual 300 MHz PowerPC processors
• 256 MB DDR memory
• 2MB SRAM (accessible from host and NIC)
• Serial port for debugging
• Descriptor control system
• Hardware Acceleration
• MAC / DMA controllers
• TCP Checksum Offloading
• Hardware Event notification

• RiceNIC TCP stream throughput compared to
  commercial NIC

• Networking is an integral part of computer
  systems
• The role of a network interface is evolving
• Significant new research is changing the
  hardware/software interface between the operating
  system and the network interface card (NIC)
• Researchers need a flexible NIC to study this
  field
• RiceNIC is a reconfigurable and programmable
  Gigabit Ethernet NIC that meets these research
  needs
• NIC design is freely available for
  research/education!
• NIC provides significant computation and storage
  resources and allows the user to customize NIC
  behavior in software and hardware.

Development Platform
Device Utilization
Software Design

• Avnet Virtex-II Pro Development Board

• PowerPC processor runs custom packet-handling
  firmware
• Interfaces with MAC to send/receive packets
• Interfaces with DDR to store bulk frame data
• Interfaces with DMA engine to transfer data
  to/from host
• Custom Linux and FreeBSD device drivers

• Space for future development

Component Virtex FPGA Virtex FPGA
Slice Registers 9,089 / 27,392 33
4 input LUTs 11,811 / 27,392 43
BRAMs 51 / 136 37
Occupied Slices 9,164 / 13,696 66
Global Clocks 10 / 16 62
Clock Managers 5 / 8 62
Gate Count 3,944,049 3,944,049
System Architecture
Virtex FPGA Placement
PCI DMA Engine
Ethernet MAC
DDR Controller
NIC Control Data Bus
PowerPCProcessors