Language for Instruction Set Architectures

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Language for Instruction Set Architectures

• Nakul Garg

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Outline of the presentation

• Firstly I have discussed what was the motive
  behind LISA
• Then I have discussed how LISA specifies an
  architecture
• Lastly I have discussed what was my work in the
  summer training

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ASIP methodology

• Architecture exploration
• Architecture implementation
• Software application tools
• System integration and verification

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Motivation for LISA

• LISA was developed for the automatic generation
  of consistent software development and
  synthesizable HDL code.
• A LISA description covers the instruction-set,
  the behavioral and the timing model of the
  underlying hardware.
• Thus it provides all information for the
  generation of complete set of software
  development tools.

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LISA description components

• LISA descriptions are composed of resources and
  operations.
• Resources represent the storage objects of the
  hardware architecture which capture the state of
  the system.
• Operations specify the behavior, the structure,
  and the instruction set of the programmable
  architecture.

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Requirements to be satisfied

• The process of generating software development
  tools and synthesizing the architecture requires
  information on architectural properties and
  instruction set definitions.
• These requirements can be grouped into different
  architectural models.
  
  

1.Memory model 2.Resource model
3.Instruction set model 4.Behavioral
model 5.Timing model
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Memory model

• The memory model lists the registers and memories
  of the system. From this model,
• Compiler gets information on available registers
  and memory spaces.The memory configuration is
  provided to perform object code linking.
• Debugger gets to know the storage elements which
  represent the state of the processor
• HDL code generator derives the basic architecture
  structure.

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How LISA provides memory model

• The resource section lists the definitions of all
  objects which are required to build the memory
  model.

RESOURCE PROGRAM_COUNTER int PC REGISTER
signed int R0..7 DATA_MEMORY signed int
RAM0..255 PROGRAM_MEMORY unsigned int
ROM0..255 PIPELINE ppu_pipe FI ID EX
WB PIPELINE_REGISTER IN ppu_pipe bit6
Opcode short operandA short operandB
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Resource model

• The resource model describes the available
  hardware resources and the resource requirements
  of operations.
• Resources can be accessed by one operation at a
  time. The instruction scheduling of the
  instructions depend on this information.
• The HDL code generator uses this information for
  resource conflict resolution

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How LISA specifies resource model

• The resource section provides information about
  the availability of hardware resources.
• The behavior section within operations announces
  the use of processor resources.

RESOURCE REGISTER unsigned int R0..7
DATA_MEMORY signed int RAM0..15 OPERATION
NEG_RM BEHAVIOR USES (IN R OUT RAM)
RAMaddress (-1) Rindex

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Instruction set model

• The instruction set model identifies the valid
  combinations of hardware operations and
  admissible operands.
• It is expressed by the assembly syntax,
  instruction word coding, and the specification of
  legal operands and addressing modes for each
  operation.
• Compilers and assemblers can identify
  instructions based on this model.
• The same information is used in the reverse
  process of decoding and disassembling.

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How LISA incorporates Instruction Set model

• In LISA, the instruction set model is captured
  within operations.Within an operation,
• CODING section describes the binary image of the
  instruction word.
• SYNTAX section describes the assembly syntax of
  the instructions, operands and execution modes.

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An illustration

• OPERATION COMPARE_IMM
• DECLARE
• LABEL index
• GROUP src1, dest register
• CODING 0b10011 index0bx5 src1 dest
• SYNTAX CMP src1 , index , dest
• BEHAVIOR
• / C-code /
• OPERATION register
• DECLARE LABEL index
• CODING index 0bx4
• SYNTAX R indexU
• EXPRESSION Rindex

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Behavioral model

• The behavioral model abstracts the activities of
  hardware structures to operations changing the
  state of the processor for simulation purposes.
• The abstraction level of this model can range
  widely between the hardware implementation level
  and HLL level.

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How LISA incorporates behavioral model

• The BEHAVIOR and EXPRESSION sections within LISA
  operations describe components of the behavioral
  model.
• The behavior section contains arbitrary C-code
  which is executed during simulation.
• The expression section defines the operands and
  execution modes used in the context of
  operations.

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An illustration

• OPERATION register
• DECLARE LABEL index
• CODING index0bx4
• EXPRESSION Rindex
• OPERATION ADD
• DECLARE GROUP src1, src2, dest register
  
• CODING 0b010010 src1 src2 dest
• BEHAVIOR
• / C-code /
• dest src1 src2
• saturate(dest)

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The timing model

• The timing model specifies the activation
  sequence of hardware operations and units.
• The instruction latency information lets the
  compiler find an appropriate schedule and
  provides timing relations between operations for
  simulation and implementation

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How LISA incorporates timing model

• Pipelines are declared in resource section
• Operations are assigned to pipeline stages by
  using the keyword IN and providing the name of
  the pipeline stage.
• OPERATION name_of_operation IN ppu_pipe.EX
• The ACTIVATION section in the operation
  description is used to activate other operations
  in the context of the current instruction.

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An illustration

• RESOURCE
• PIPELINE ppu_pipe FI ID EX WB
• OPERATION CORDIC IN ppu_pipe.EX
• ACTIVATION Writeback
• BEHAVIOR
• PIPELINE_REGISTER(ppu_pipe, EX/WB).ResultE
  cordic()
• OPERATION Writeback IN ppu_pipe.WB
• BEHAVIOR
• Rvalue PIPELINE_REGISTER(ppu_pipe,
  EX/WB).ResultE

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Micro-arch model

• The micro-architectural model allows grouping of
  hardware operations to functional units
• It contains the exact micro-architectural
  implementation of structural components like
  adders and multipliers.
• This enables the HDL generator to generate the
  appropriate HDL code from a more abstract
  specification.
• In LISA we use the keyword ENTITY to model FUs
  which do more than one operation in resource
  section
• ENTITY Alu
• Add, Sub

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Summary of requirements
Memory resource instruction
behavior timing micro-arch model
model set model model
model model
coding
activation
syntax
RESOURCE
behavior
OPERATION
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A look at operation hierarchy

• As we have seen in illustrations, operation
  hierarchies are built by referencing other
  operations. In all sections, references to other
  operations is possible.

Referencing operation Referenced
operation CODING
CODING SYNTAX
SYNTAX EXPRESSION
EXPRESSION BEHAVIOR
EXPRESSION, BEHAVIOR ACTIVATION
BEHAVIOR, ACTIVATION
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Architecture generated by LISA

• Coarse processor structure such as register-set,
  pipeline, pipeline-registers test-interface.
• Instruction-decoder setting data control
  signals which are carried through the pipeline
  and activate the respective fuctional units
  executed in context of the decoded instuction.
• Pipeline controller handling different pipeline
  interlocks, pipeline register flushes and
  supporting mechanisms like data-forwarding

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Original memory accessing

• In existing LISA models, calls to memory were
  blocking,i.e., a memory read request or a write
  request did not return till the value was made
  available.
• So in cycle true models, where you want
  simulation to proceed cycle-accurately , the
  cycles which were required in case of failed
  accesses were missed.

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The task

• Basically, I just had to provide a mechanism for
  explicit stalling of the processor in the case of
  a denied memory access.
• LISA provides stall functionality to the extent
  that an operation can execute a function
  pipeline_register(pipe, register).stall() which
  stalls the register for the next control step.

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Two approaches

• Delayed activation
• raising a global signal which is serviced by
  operation main which completes the task and
  keeping the processor stalled till the request is
  granted

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C54x pipeline
AC stage activates operations in RD and EX stage
PF
FE DC
AC RD
EX
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C54x pipeline required for delayed reactivation
approach
RD operation reactivating itself till read is
successful
PF
FE DC
AC RD
EX
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C54x pipeline required for correct scheduling of
operations
RD/EX stalled so that activation of EX is not
executed
PF
FE DC
AC RD
EX
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Missed stalls and flushes

• As previously reported, a stall/flush executed by
  an operation is valid for next control step.
• So stall/flush will be missed if a memory access
  is denied in the same control step in which the
  stall/flush was requested by some other
  operation.
• This stall/flush should be executed when the
  stall due to memory is gone.

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Result

• To get rid of this problem, I used global
  stall/flush flags which are serviced by OPERATION
  main.
• After this modification, the explicit stalling
  succeeded, and a cycle accurate model of C54x is
  now functional.

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References

• A. Hoffmann, H.meyr, et al. A novel methodology
  for the design of application specific integated
  processers(ASIP) using a machine description
  language.
• LISA 2.0 Language Reference manual