New Opportunities for Computer Architecture Research Using High-Density FPGAs and Design Tools

1
New Opportunities for Computer Architecture
Research Using High-Density FPGAs and Design Tools
Nahi Abdul-Ghani, Patrick Akl, Mohammad
El-Majzoub, Maroulla Haddad, Siba Harb, Marwan
Simaan, and Mazen A. R. Saghir nha15,pea02,mte01,
mgh09,shh15,mjs15,mazen_at_aub.edu.lb Department of
Electrical and Computer Engineering American
University of Beirut
Designing an IEEE-754-compliant floating-point
unit (FPU) for the Xilinx MicroBlaze soft CPU
core. Supporting basic floating-point operations
addition, subtraction, multiplication, division,
and square root. Studying the architectural
implications and performance/area tradeoffs of
three organizational models.
Accomplishments Functional VHDL models of
add/subtract unit (optimized dual-path model)
multiply unit divide unit (Newton-Raphson
algorithm). Challenges Minimizing area using
Virtex-IIs on-chip resources (e.g. multipliers,
memory blocks) integrating FPU with MicroBlaze
datapath. Next Steps Square root, synthesis,
datapath integration, testing, benchmarking.
Standalone MicroBlaze floating-point support in
software.
Floating-point co-processor connected to the
MicroBlaze using Fast Simplex Links (FSLs).
Integrated FPU
Developing a datapath generator for a VLIW-based
Application-Specific Instruction Set Processor
(ASIP). Configurable datapath (data widths,
functional units, register files, pipeline
stages. Read architectural parameters from a
configuration file, and generate synthesizable
VHDL code. Rely on design tool for synthesis,
technology mapping, placement, and routing.
Accomplishments Tool generating VHDL code for
main functional units. Challenges Minimizing
area using Virtex-IIs on-chip resources (e.g.
multipliers, memory blocks) where possible. Next
Steps Control and pipeline generation
supporting custom units synthesis testing.