Asian Test Symposium 1999 Panel Discussion Nanometer Technology, How to Test

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Asian Test Symposium 1999Panel Discussion
Nanometer Technology, How to Test?

• Chauchin Su
• Department of Electrical Engineering
• National Central University
• Chung-Li, Taiwan 32054
• http//www.ee.ncu.edu.tw/ccsu

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New Millennium Test
Don't Worry
Its no big deal.
Be Happy!
If it is, we are the experts.
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New Millennium Test
However,
Be Prepared!
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ITRS 1999 Summary
T Nodes Gate L (nm) DRAM HPitch Memory
Size Logic Size (Tx) On-Chip Clk Off-Chip Clk IC
Pins Min Vdd
2015 25 35 - 390M 16824 1852 3642 0.4
1999 140 180 256M 6.2M 1250 480 810 1.8V
2001 120 153 1G 10M 1500 785 900 1.5V
2003 100 130 1G 18M 2100 885 1100 1.2V
2006 70 100 4G 39M 3500 1035 1500 1.2V
2009 50 70 16G 84M 6000 1285 2000 0.9V
2012 35 50 64G 180M 10000 1540 2700 0.6V
High performance otherwise cost performance
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ITRS 1999 - VLSI Technology Grand Challenges

• The ability to continue affordable scaling
• Affordable lithography at and below 100nm
• New material and structure
• GHz frequency operation on- and off-chip
• Metrology and Test
• The research and development challenge

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ITRS 1999 - Overall Test/Diagnosis Ability
250nm
Increase on chip test BIST/DFT
200nm
Standard Test Method for Core Based Designs
150nm
Timing/At-Speed Test at Core Level
100nm
50nm
1997
1999
2001
2003
2006
2009
2012
P1500 VSI
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ITRS 1999 - Test Difficult Challenges
250nm
Fault Model Rules to Test Standard Test
Software DFT Failure Analysis
200nm
Mixed Signal Instrument BIST/DFT Probe Test
Socket IDDQ Testing Test Development Time
150nm
100nm
50nm
1997
1999
2001
2003
2006
2009
2012
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ITRS 1999 - Test Difficult Challenges (gt 100nm)

• BIST DFT Test equipment cost rise to 20M and
  yields fall to zero unless there is increased use
  of DFT/BIST.
• Probe Socket The major roadblock will be the
  need for high frequency, high pin count probes
  and sockets.
• Mixed Signal Instrument More bandwidth, higher
  sample rates and lower noise for RF/audio ICs.
• IDDQ Testing Circuit partitioning and built-in
  current sensors are needed for gt 10M Tx.
• Test Development Time Mixed signal test
  development time must be reduced, analog DFT and
  BIST are key area for research.

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ITRS 1999 - Test Difficult Challenges (lt 100nm)

• Fault Model Stuck-at fault model is less
  effective, new model is needed.
• Rules to Test Tools and rules to automatically
  check the correctness of test program and DFT.
• Standard Test Software Common definition of test
  tools nomenclature to make tests portable are
  needed.
• DFT New DFT techniques other than SCAN and BIST,
  break through for control and observation are
  needed.
• Failure Analysis 3D CAD and FA systems for
  isolation of defects in multi-layer metal
  processes.

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ITRS 1999 - Revisit
T Nodes Gate L (nm) DRAM HPitch Memory
Size Logic Size (Tx) On-Chip Clk Off-Chip Clk IC
Pins Min Vdd
2015 25 35 - 390M 16824 1852 3642 0.4
1999 140 180 256M 6.2M 1250 480 810 1.8V
2001 120 153 1G 10M 1500 785 900 1.5V
2003 100 130 1G 18M 2100 885 1100 1.2V
2006 70 100 4G 39M 3500 1035 1500 1.2V
2009 50 70 16G 84M 6000 1285 2000 0.9V
2012 35 50 64G 180M 10000 1540 2700 0.6V
Large Tx Count, High Speed, High Pin Count
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Large Circuit Size

• What does the Large Circuit Size really mean?
• Its mainly the size not the complexity.
• Memory chips are large in size but not in
  complexity.
• DFT and parallel test fixture can help.
• Its mainly the parallelism not the complexity.
• Multi processor and parallel computing are the
  issue but not the complexity.
• C Testable or FPGA test algorithm can help
• Its mainly the Integration not the complexity.
• System on Chip (SoC) realize a board on a chip.
• How do you test a circuit board or a system?

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High Pin Counts - Current Status

• High package cost and low packaging yield
• High PCB cost and low mounting yield
• High ATE pin counts
• Expensive ATE - 20M US
• Will the pin count increase continuously?
• Does it make sense for integration to increase
  the complexity?
• Does a system require a large number of real
  world interface?
• The pin count will grow then shrink.

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High Pin Counts - Current Status
Monitor
KeyBoard
Mouse
P Ports
S Ports
USB
Processor
Processor
Processor
Processor
Processor
Processor
MMU
Cache
BIOS
CPU
PU
RAM
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High Pin Counts - New Millennium
Monitor
KeyBoard
Mouse
P Ports
S Ports
USB
Processor
Processor
Processor
Processor
Processor
Processor
SoC
MMU
Cache
BIOS
CPU
PU
RAM
Processor
Processor
Processor
Processor
Processor
Processor
Audio
FireWire
Ethernet
USB
Floppy
HardDisk
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Complicated System - SoC
Analog
ADC
MPU
RAM
Analog
DAC
Digital
DSP
ROM
External Instrument
Loop Back

• Specialized DFT and BIST for individual modules
• DSP and MPU are the resources for analog testing
• System level functional verification and
  parametric testing
• IEEE 1149 family provides a fundamental
  architecture for SoC DFT/BIST.
• The concept is how do you test a circuit board.

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High Speed - GHz in New Millennium

• Greater than 1GHz in the new millennium
• Transmission line effects for on-chip buses.
• Transmission line effects for off-chip
  interconnects.
• GHz measurement instrument?
• GHz ATE?
• On-chip timing verification?

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High Speed - The Test Yield Drop
1.6ns
250nm
1.2ns
200nm
0.8ns
150nm
0.4ns
100nm
50nm
1997
1999
2001
2003
2006
2009
2012
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High Speed - The Test Yield Drop
1.8ns
2ns
0.2ns
Device Period 2ns Timing Accuracy 0.2ns
(1s) Timing Test at 1.8ns Guard Band
0.2ns Yield Loss 5
Device Period 0.2ns Timing Accuracy 0. 2ns
(1s) Timing Test at ? Guard Band 0.2ns Yield
Loss 50
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Timing Test
Timing Test and Timing Measurement is the
Bottleneck.
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Conventional Timing Test
Clk
Din
Dout
D
Q
Din
Clk
Dout
Time Gen 1
Timing Markers and Strobes
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New Millennium Timing Test
Lee (1997,1998) and Kaminska (1998) Digital
Oscillation Test
Frequency Counter
CUT
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New Millennium Timing Test
Su, etc., All Digital Delay and Crosstalk
Measurement for On-Chip Buses, to appear in
DATE 2000.
Counter
Clock
Input Data
Output Data
Delay Phase
Delay Count
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New Millennium Timing Test

• Single shot timing is extremely difficult to
  test.
• Statistical Timing Measurement is the way.
• Use Time to trade for Accuracy.
• Repeat the events
• Measure the timing statistically
• The techniques have been used in ADC such as
  dual-slop, successive approximation, SD
  modulation.

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New Millennium Test
Design and Test?
Analog
ADC
MPU
RAM
Analog
DAC
Digital
DSP
ROM
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New Millennium Test
Join the ATS 2000
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ATS 2000
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New Millennium Test
Design and Test?
Analog
ADC
MPU
RAM
Analog
DAC
Digital
DSP
ROM
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New Millennium Tes - Problem Fomulation
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New Millennium Test - Break Through Innovation
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New Millennium Test - In Depth Investigation
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New Millennium Test - Multidiscipline cooperation
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New Millennium Test -
Horizontal Vertical Integration
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New Millennium Test - Challenge the Summit
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New Millennium Test - The Lucrative Reward