LECTURE 2: DSP Architectures

1
LECTURE 2 DSP Architectures
EECS 318 CADComputer Aided Design
Instructor Francis G. Wolff wolff_at_eecs.cwru.edu
Case Western Reserve University This
presentation uses powerpoint animation please
viewshow
2
Pipelining (Designing,M.J.Quinn, 87)
Instruction Pipelining is the use of pipelining
to allow more than one instruction to be in some
stage of execution at the same time.
Cache memory is a small, fast memory unit used as
a buffer between a processor and primary memory
Ferranti ATLAS (1963)? Pipelining reduced the
average time per instruction by 375? Memory
could not keep up with the CPU, needed a cache.
3
Pipelining versus Parallelism (Designing,M.J.Quin
n, 87)
Most high-performance computers exhibit a great
deal of concurrency.
However, it is not desirable to call every modern
computer a parallel computer.
Pipelining and parallelism are 2 methods used to
achieve concurrency.
Pipelining increases concurrency by dividing a
computation into a number of steps.
Parallelism is the use of multiple resources to
increase concurrency.
4
Pipelining is Natural!

• Laundry Example
• Ann, Brian, Cathy, Dave each have one load of
  clothes to wash, dry, and fold
• Washer takes 30 minutes
• Dryer takes 30 minutes
• Folder takes 30 minutes
• Stasher takes 30 minutesto put clothes into
  drawers

5
Sequential Laundry
2 AM
12
6 PM
7
8
11
1
10
9
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
T a s k O r d e r
Time

• Sequential laundry takes 8 hours for 4 loads
• If they learned pipelining, how long would
  laundry take?

6
Pipelined Laundry Start work ASAP
2 AM
12
6 PM
8
1
7
10
11
9
Time
T a s k O r d e r
Pipelined laundry takes 3.5 hours for 4 loads!
7
Pipelining Lessons

• Pipelining doesnt help latency of single task,
  it helps throughput of entire workload
• Multiple tasks operating simultaneously using
  different resources
• Potential speedup Number pipe stages
• Pipeline rate limited by slowest pipeline stage
• Unbalanced lengths of pipe stages reduces speedup
• Time to fill pipeline and time to drain it
  reduces speedup
• Stall for Dependences

6 PM
7
8
9
Time
T a s k O r d e r
8
Memory Hierarchy
Registers
More Capacity
Faster
Cheaper
Pipelining
Cache memory
Primary real memory
Virtual memory (Disk, swapping)
9
Ideal Pipelining
Assume instructions are completely independent!
IF
DCD
EX
MEM
WB
IF
DCD
EX
MEM
WB
IF
DCD
EX
MEM
WB
IF
DCD
EX
MEM
WB
IF
DCD
EX
MEM
WB
Maximum Speedup ? Number of stages Speedup
??Time for unpipelined operation
Time for longest stage
10
(No Transcript)
11
(No Transcript)
12
(No Transcript)
13
(No Transcript)
14
(No Transcript)
15
(No Transcript)
16
(No Transcript)
17
(No Transcript)
18
(No Transcript)
19
(No Transcript)
20
(No Transcript)
21
(No Transcript)
22
(No Transcript)
23
(No Transcript)
24
(No Transcript)
25
(No Transcript)
26
(No Transcript)
27
(No Transcript)
28
(No Transcript)
29
(No Transcript)
30
(No Transcript)
31
(No Transcript)
32
(No Transcript)
33
(No Transcript)