AN INNOVATIVE MEANS OF GENERATING SINUSOIDAL WAVEFORMS FOR POWER ELECTRONIC APPLICATIONS

1

• AN INNOVATIVE MEANS OF GENERATING SINUSOIDAL
  WAVEFORMS FOR
  POWER ELECTRONIC APPLICATIONS
• BY
• SERKAN PAKI SEDELE

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OUTLINE

• INTRODUCTION
• DETERMINATION OF SUITABLE TOPOLOGY FOR INVERTER
  PART
• INTEGRATION OF BUCK CONVERTER AND H-BRIDGE
  INVERTER UNDER A SPECIFIC LOAD
• COMPUTER SIMULATIONS
• CIRCUIT MODIFICATIONS

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INTRODUCTION

• The purpose of this study is to generate
  sinusoidal waveforms in an innovative means which
  is to obtain sinusoidal waveforms from full
  rectified sinusoids. At this point, the overall
  circuit is thought to be composed of two parts
  connected in a cascade manner.
• The first part should produce full-rectified
  sinusoids. A DC-to-DC converter (either buck or
  buck-boost topology) is considered to be used.
  (If necessary some modifications will be made on
  these topologies).
• The second part of the circuit, which can be
  called as the inverter part, should form
  sinusoidal waveform from full-rectified
  sinusoids. In the next section (theoretical
  study), the candidate topologies for the inverter
  part are examined mode by mode in detail.

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INTRODUCTION
5
INTRODUCTION
6
Determination of Suitable Topology for Inverter
Part

• The first topology consists of two tyristors and
  two diodes as shown in figure

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Determination of Suitable Topology for Inverter
Part

• The second topology also consists of two
  tyristors and two diodes but in a different
  arrangement as shown in figure

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Determination of Suitable Topology for Inverter
Part

• The third topology consists of four tyristors

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Determination of Suitable Topology for Inverter
Part

• The fourth topology is a modified version of the
  four thyristorized circuit. At this time four
  anti-parallel diodes are added as shown in figure

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Determination of Suitable Topology for Inverter
Part

• The fifth topology consists of two tyristors and
  two transistors as shown in figure

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Determination of Suitable Topology for Inverter
Part

• The sixth topology consists of four transistors.

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Determination of Suitable Topology for Inverter
Part

• The lagging current commutation problem will be
  solved by providing a path to this current when
  the switches change state.

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Determination of Suitable Topology for Inverter
Part

• The voltage and the current are positive. TR1 and
  TR4 are on. The load voltage is the input voltage
  minus the voltage drops on the transistors

Mode-1
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Determination of Suitable Topology for Inverter
Part

• The voltage is negative but the current is still
  positive. TR1 and TR4 are turned off. The current
  continues to flow through D2 and D3 and even if
  the gate signals are applied, TR2 and TR3 can not
  be turned on.

Mode-2
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Determination of Suitable Topology for Inverter
Part

• Both the voltage and the current are negative.
  TR2 and TR3 are on. The load voltage is the
  reverse of the input voltage

Mode-3
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Determination of Suitable Topology for Inverter
Part

• The voltage is now positive but the current is
  still negative. TR2 and TR3 are turned off. The
  current continues to flow through D1 and D4 and
  even the gate signals are applied, TR1 and TR4
  can not be turned on. The load voltage is the
  input voltage

Mode-4
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Determination of Suitable Topology for Inverter
Part

• The theoretical voltage and current waveforms
  indicating the operation modes are as shown in
  figure

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INTEGRATION OF BUCK CONVERTER AND H-BRIDGE
INVERTER UNDER A SPECIFIC LOAD

• In this part the two distinct circuit which are
  the buck converter and the H-bridge, are
  connected together to form a sinusoidal wave
  shape. To obtain a satisfactory result
  (especially for the dynamic response) the input
  voltage to the H-bridge (output voltage of the
  buck converter), will be controlled in a closed
  loop system by taking feed-back from the
  capacitor voltage.

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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD
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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD

• Determination of the Buck Converter Parameters
• Let R 15 ? and L 25 mH
• XL 15j7.854 16.93 ? at 50Hz
• Let the switching frequency be 60 kHz
• For continuous inductance current,
• For the worst case, D0
• Lmin 130 ?H

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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD

• Determination of the Buck Converter Parameters
• For 1 output voltage ripple, the capacitor
  value should be,
• For the worst case, D0
• C ? 27 ?F

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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD

• Determination of the Control Circuit Parameters
• The capacitor voltage should track the reference
  voltage which is full-rectified sinusoids. So the
  capacitor voltage and the reference voltage are
  compared. Then the error is compensated by the
  help of a PI controller. The control signal is
  then applied to a PWM generator and the resultant
  signals become the switching signals of the buck
  converters controllable switch.
• In order to determine the controller parameters,
  we should first obtain a transfer function of the
  overall system from the small signal averaged
  circuit.

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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD

• Determination of the Control Circuit Parameters
• Where Vo Capacitor Voltage Vc Input of the
  PWM generator
• Vs System Input Voltage

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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD

• Determination of the Control Circuit Parameters
• Let the crossover frequency be fco10 kHz
• The frequency characteristics of the system is
  obtained with MATLAB as shown in figure

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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD

• Determination of the Control Circuit Parameters

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INTEGRATION OF BUCK CONVERTER AND
H-BRIDGE INVERTER UNDER A SPECIFIC LOAD

• Determination of the Control Circuit Parameters
• From the bode diagram we can see that, the system
  gain at 10 kHz (62800 rad/s) is -14.6 dB
  with a phase angle of -95.8?. The compensated
  error amplifier should have a gain of 14.6 dB at
  10 kHz to make the loop gain 0 dB. Also phase
  margin is adjusted to be ? 46? in order to assure
  the stability.
• So the resistance and the capacitance values of
  the compensated error amplifier are chosen and
  calculated as,
• R1 1k?
• R2 6k?
• C18nF
• C21nF

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COMPUTER SIMULATIONS

• Orcads Pspice is used as the circuit simulator.
  Initially the circuit is simulated for only
  resistive load (with feed-back) control). The
  result is shown in figure.

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COMPUTER SIMULATIONS
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COMPUTER SIMULATIONS

• Then a two stepped process is followed for
  inductive load. At the first step, feed-forward
  control, and at the second step, feed-back
  control is used. The outputs of the simulation
  are given in the figures respectively.

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COMPUTER SIMULATIONS
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COMPUTER SIMULATIONS
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CIRCUIT MODIFICATIONS

• In order to eliminate the over-voltage on the
  capacitor produced as a result of the reactive
  current, one more switch is added to the circuit.

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CIRCUIT MODIFICATIONS

• The new waveforms are

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CIRCUIT MODIFICATIONS
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CIRCUIT MODIFICATIONS
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CIRCUIT MODIFICATIONS
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CIRCUIT MODIFICATIONS