TwoChip Intercom

1
Two-Chip Intercom

• Josie Ammer, Per Bjureus, Fred Burghardt,
  Fernando De Bernardinis, Chunlong Guo, Suet Fei
  Li, Sue Mellers,Vandana Prabhu, Marco Sgroi, Mike
  Sheets, Julio L. Silva Jr., Arvind
  Thirunarayananan
• Jan Rabaey Alberto Sangiovanni-Vincentelli

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Intercom

• Wireless network of approx. 40 Remote Terminals
  (RT)
• Network coordinated by a Base Station (BS)
• Medium Access Control TDMA (20 slots)
• Type of data voice
• Type of services Connection, Multi-way
  Conference, Users Query

RT/BS
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Intercom Board
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Two-Chip Intercom
Program-mable logic
Software running on processor
Custom analog circuitry
Mixed analog/ digital
Fixed logic
Protocol
ADC
Digital Baseband processing
Analog RF
DAC
Chip 2
Chip 1
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Protocol Layers and Interfaces
Voice samples
Service Requests
User Interface Layer
UI
Mulaw
Mulaw
Transport Layer
Transport
Mac Layer
MAC
Filter
Error Control Layer
Transmit
Receive
Synchronization Layer
Synchronization
Tx_data
Rx_data
Tx/Rx
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Target Implementation Platform
Memory Sub-system
Tensilica Embedded Proc.
Sonics Backplane
Programmable Protocol Stack
ConfigurableLogic (Physical Layer)
Baseband Processing
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Sonics Bus Model
Arbiter
IClk
SBClk
SBClk
TClk
Initiator Core
Initiator Agent
Interconnect
Target Agent
Target Core
OCP
OCP
Processor
Clock synch., SB handshaking
Clock synch., SB handshaking
Memory, I/O ports
Pipelined commands Posted writes Selectable read
latency
Sonics SiliconBackplane
Sender
Receiver

• Flexible bandwidth arbitration model
• TDMA slot map gives slot owner right of refusal
• Unowned/unused slots fall to round-robin
  arbitration
• SBClk typically different from IClk and TClk so
  synchronization required
• Latency after slice granted is user-specified
  between 2-7 SBClk cycles

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Describing The Protocol Stack
Development time 4 person-month

• Cadence VCC Polis
• Model of Computation CFSM

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Mapping The Protocol Stack
Architecture Exploration 4 archs. per
day Convergence 1 week!
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Physical to Protocol Interface Design
Goal Decouple physical layer and protocol layer
development
Step 1 Develop radio operating mode to match
application requirements Step 2 Define interface
signals and behavior with no associated timing
constraints (design based on interface to a
commercially available radio) Step 3 Create
wrapper for existing physical layer that
implements the interfaceCreate wrapper for
existing protocol layer that implements the
interface Step 4 Determine timing information
and constraints using physical layer simulations
and analysis
Physical Layer
Protocol and above
MACLayer
TransLayer
App.Layer
Base-band
RF
SynchLayer
UI
Chip 2
Chip 1
Proxim-like wrapper
7 wire PPI (physical-to-protocol interface)
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Physical Layer Development
Stage 1 floating point blocksStage 2 fixed
point blocks
Stage 1 Model components in MATLAB tools at
appropriate granularities Behavioral level
Simulink -- RF, ADC, DACStructural level in
Simulink -- Digital BB (initially in floating
point) Structural level in Stateflow --
Control Verify Basic functionality. Determine
timing information and constraints Stage 2
Convert underlying Simulink structural blocks
(manually) to fixed point/bit-true Verify Bit
width effect on performance Stage 3 Synthesize
to HW (automatic synthesis path Simulink to
HW) Verify Implementation meets timing
requirements
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Physical Layer Timing Analysis

• Analysis of simulations yields high-level numbers
  (such as radio turnaround time and transmission
  latency)

Tool Microsoft Excel