ECE 545 Lecture 5 Finite State Machines

1
ECE 545Lecture 5 Finite State Machines
Mixed Style RTL Modeling
2
Resources

• Volnei A. Pedroni, Circuit Design with VHDL
• Chapter 8, State Machines
• Sundar Rajan, Essential VHDL RTL Synthesis
• Done Right
• Chapter 6, Finite State Machines
• Chapter 10, Getting the Most from Your State
• Machine
• Stephen Brown, Zvonko Vranesic, Digital Logic
  with VHDL Design
• Chapter 7.14.2, Simple Processor (handout)

3
Structure of a Typical Digital System
Data Inputs
Control Inputs
Control Signals
Execution Unit (Datapath)
Control Unit (Control)
Data Outputs
Control Outputs
4
Execution Unit (Datapath)

• Provides All Necessary Resources and
  Interconnects Among Them to Perform Specified
  Task
• Examples of Resources
• Adders, Multipliers, Registers, Memories, etc.

5
Control Unit (Control)

• Controls Data Movements in Operational Circuit by
  Switching Multiplexers and Enabling or Disabling
  Resources
• Follows Some Program or Schedule
• Often Implemented as Finite State Machine
• or collection of Finite State Machines

6
Finite State Machines (FSMs)

• Any Circuit with Memory Is a Finite State Machine
• Even computers can be viewed as huge FSMs
• Design of FSMs Involves
• Defining states
• Defining transitions between states
• Optimization / minimization
• Above Approach Is Practical for Small FSMs Only

7
Moore FSM

• Output Is a Function of Present State Only

Next State function
Inputs
Next State
Present State
Present StateRegister
clock
reset
Output function
Outputs
8
Mealy FSM

• Output Is a Function of a Present State and Inputs

Next State function
Inputs
Next State
Present State
Present StateRegister
clock
reset
Output function
Outputs
9
Moore Machine
transition condition 1
state 2 / output 2
state 1 / output 1
transition condition 2
10
Mealy Machine
transition condition 1 / output 1
state 2
state 1
transition condition 2 / output 2
11
Moore vs. Mealy FSM (1)

• Moore and Mealy FSMs Can Be Functionally
  Equivalent
• Equivalent Mealy FSM can be derived from Moore
  FSM and vice versa
• Mealy FSM Has Richer Description and Usually
  Requires Smaller Number of States
• Smaller circuit area

12
Moore vs. Mealy FSM (2)

• Mealy FSM Computes Outputs as soon as Inputs
  Change
• Mealy FSM responds one clock cycle sooner than
  equivalent Moore FSM
• Moore FSM Has No Combinational Path Between
  Inputs and Outputs
• Moore FSM is more likely to have a shorter
  critical path

13
Moore FSM - Example 1

• Moore FSM that Recognizes Sequence 10

reset
S0 No elements of the sequence observed
S2 10 observed
S1 1 observed
Meaning of states
14
Mealy FSM - Example 1

• Mealy FSM that Recognizes Sequence 10

0 / 0
1 / 0
1 / 0
S0
S1
reset
0 / 1
S0 No elements of the sequence observed
S1 1 observed
Meaning of states
15
Moore Mealy FSMs Example 1
clock
0 1 0 0
0
input
S0 S1 S2 S0
S0
Moore
S0 S1 S0 S0
S0
Mealy
16
FSMs in VHDL

• Finite State Machines Can Be Easily Described
  With Processes
• Synthesis Tools Understand FSM Description If
  Certain Rules Are Followed
• State transitions should be described in a
  process sensitive to clock and asynchronous reset
  signals only
• Outputs described as concurrent statements
  outside the process

17
Moore FSM
process(clock, reset)
Next State function
Inputs
Next State
Present StateRegister
clock
Present State
reset
concurrent statements
Output function
Outputs
18
Mealy FSM
process(clock, reset)
Next State function
Inputs
Next State
Present State
Present StateRegister
clock
reset
Output function
Outputs
concurrent statements
19
FSM States (1)
architecture behavior of FSM is type state
is (list of states) signal FSM_state
state begin process(clk, reset)
begin if reset 1 then
FSM_state lt initial state
elsif (clock 1 and clockevent) then
case FSM_state is
20
FSM States (2)
case FSM_state is when state_1
gt if transition condition 1
then FSM_state lt
state_1 end if
when state_2 gt if transition
condition 2 then FSM_state
lt state_2 end if end
case end if end process
21
Moore FSM - Example 1

• Moore FSM that Recognizes Sequence 10

reset
22
Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2) SIGNAL Moore_state
state U_Moore PROCESS (clock,
reset) BEGIN IF(reset 1) THEN Moore_state
lt S0 ELSIF (clock 1 AND clockevent)
THEN CASE Moore_state IS WHEN S0 gt IF
input 1 THEN Moore_state
lt S1 ELSE
Moore_state lt S0 END IF
23
Moore FSM in VHDL (2)

• WHEN S1 gt
• IF input 0 THEN
• Moore_state
  lt S2
• ELSE
• Moore_state
  lt S1
• END IF
• WHEN S2 gt
• IF input 0 THEN
• Moore_state
  lt S0
• ELSE
• Moore_state
  lt S1
• END IF
• END CASE
• END IF
• END PROCESS
• Output lt 1 WHEN Moore_state S2 ELSE 0

24
Mealy FSM - Example 1

• Mealy FSM that Recognizes Sequence 10

0 / 0
1 / 0
1 / 0
S0
S1
reset
0 / 1
25
Mealy FSM in VHDL (1)
TYPE state IS (S0, S1) SIGNAL Mealy_state
state U_Mealy PROCESS(clock,
reset) BEGIN IF(reset 1) THEN Mealy_state
lt S0 ELSIF (clock 1 AND clockevent)
THEN CASE Mealy_state IS WHEN S0 gt
IF input 1 THEN
Mealy_state lt S1 ELSE
Mealy_state lt S0
END IF
26
Mealy FSM in VHDL (2)

• WHEN S1 gt
• IF input 0 THEN
• Mealy_state
  lt S0
• ELSE
• Mealy_state
  lt S1
• END IF
• END CASE
• END IF
• END PROCESS
• Output lt 1 WHEN (Mealy_state S1 AND input
  0) ELSE 0

27
Moore FSM Example 2 State diagram
28
Moore FSM Example 2 State table
29
Moore FSM
process(clock, reset)
Input w
Next State function
Next State
Present StateRegister
Present State y
clock
resetn
Output z
concurrent statements
Output function
30
Moore FSM Example 2 VHDL code (1)
USE ieee.std_logic_1164.all ENTITY simple
IS PORT ( clock IN STD_LOGIC
resetn IN STD_LOGIC
w IN STD_LOGIC z
OUT STD_LOGIC ) END simple ARCHITECTURE
Behavior OF simple IS TYPE State_type IS (A, B,
C) SIGNAL y State_type BEGIN PROCESS (
resetn, clock ) BEGIN IF resetn '0'
THEN y lt A ELSIF (Clock'EVENT AND Clock
'1') THEN
31
Moore FSM Example 2 VHDL code (2)
CASE y IS WHEN A gt IF w '0' THEN
y lt A ELSE y lt B
END IF WHEN B gt IF w '0'
THEN y lt A ELSE y lt C
END IF WHEN C gt IF w '0'
THEN y lt A ELSE y lt C
END IF END CASE
32
Moore FSM Example 2 VHDL code (3)

• END IF
• END PROCESS
• z lt '1' WHEN y C ELSE '0'
• END Behavior

33
Moore FSM
process (w, y_present)
Input w
Next State function
Next State y_next
process (clock, resetn)
Present StateRegister
Present State y_present
clock
resetn
Output z
concurrent statements
Output function
34
Alternative VHDL code (1)
ARCHITECTURE Behavior OF simple IS TYPE
State_type IS (A, B, C) SIGNAL y_present,
y_next State_type BEGIN PROCESS ( w,
y_present ) BEGIN CASE y_present IS WHEN A
gt IF w '0' THEN y_next lt A
ELSE y_next lt B END IF
WHEN B gt IF w '0' THEN y_next lt
A ELSE y_next lt C END IF
35
Alternative VHDL code (2)
WHEN C gt IF w '0' THEN y_next lt A
ELSE y_next lt C END IF END
CASE END PROCESS PROCESS (clock,
resetn) BEGIN IF resetn '0'
THEN y_present lt A ELSIF (clock'EVENT AND
clock '1') THEN y_present lt y_next END
IF END PROCESS z lt '1' WHEN y_present C
ELSE '0' END Behavior
36
Mealy FSM Example 2 State diagram
37
Mealy FSM Example 2 State table
38
Mealy FSM
process(clock, reset)
Input w
Next State function
Next State
Present State y
Present StateRegister
clock
resetn
Output z
Output function
concurrent statements
39
Mealy FSM Example 2 VHDL code (1)
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY Mealy IS PORT ( clock IN
STD_LOGIC resetn IN
STD_LOGIC w IN
STD_LOGIC z OUT STD_LOGIC ) END
Mealy ARCHITECTURE Behavior OF Mealy IS TYPE
State_type IS (A, B) SIGNAL y State_type
BEGIN PROCESS ( resetn, clock ) BEGIN IF
resetn '0' THEN y lt A ELSIF
(clock'EVENT AND clock '1') THEN
40
Mealy FSM Example 2 VHDL code (2)

• CASE y IS
• WHEN A gt
• IF w '0' THEN
• 
  y lt A
• ELSE
• 
  y lt B
• END IF
• WHEN B gt
• IF w '0' THEN
• 
  y lt A
• ELSE
• 
  y lt B
• END IF
• END CASE

41
Mealy FSM Example 2 VHDL code (3)

• END IF
• END PROCESS
• WITH y SELECT
• z lt w WHEN B,
• z lt 0 WHEN others
• END Behavior

42
State Encoding Problem

• State Encoding Can Have a Big Influence on
  Optimality of the FSM Implementation
• No methods other than checking all possible
  encodings are known to produce optimal circuit
• Feasible for small circuits only
• Using Enumerated Types for States in VHDL Leaves
  Encoding Problem for Synthesis Tool

43
Types of State Encodings (1)

• Binary (Sequential) States Encoded as
  Consecutive Binary Numbers
• Small number of used flip-flops
• Potentially complex transition functions leading
  to slow implementations
• One-Hot Only One Bit Is Active
• Number of used flip-flops as big as number of
  states
• Simple and fast transition functions
• Preferable coding technique in FPGAs

44
Types of State Encodings (2)
State Binary Code One-Hot Code
S0 000 10000000
S1 001 01000000
S2 010 00100000
S3 011 00010000
S4 100 00001000
S5 101 00000100
S6 110 00000010
S7 111 00000001
45
A user-defined attribute for manual state
assignment
(ENTITY declaration not shown) ARCHITECTURE
Behavior OF simple IS TYPE State_type IS (A, B,
C) ATTRIBUTE ENUM_ENCODING STRING
ATTRIBUTE ENUM_ENCODING OF State_type TYPE
IS "00 01 11" SIGNAL y_present, y_next
State_type BEGIN cont ...
Figure 8.34
46
Using constants for manual state assignment (1)
ARCHITECTURE Behavior OF simple IS
SUBTYPE ABC_STATE is STD_LOGIC_VECTOR(1 DOWNTO
0) CONSTANT A ABC_STATE "00" CONSTANT
B ABC_STATE "01" CONSTANT C ABC_STATE
"11" SIGNAL y_present, y_next
ABC_STATE BEGIN PROCESS ( w, y_present
) BEGIN CASE y_present IS WHEN A gt IF
w '0' THEN y_next lt A ELSE y_next lt B
END IF cont
47
Arrays
48
Arrays of std_logic_vectors
32
L(0)
1
REP_BLOCK
L(1)
32
REP_BLOCK
2
32
L(2)
3
REP_BLOCK
L(3)
32
. . .
. . . . . . . . . .
L(M-1)
32
M
REP_BLOCK
32
L(M)
49
Arrays of std_logic_vectors

• TYPE sig_array IS ARRAY(0 TO M) OF
  STD_LOGIC_VECTOR(31 DOWNTO 0)
• SIGNAL L sig_array
• BEGIN
• L(0) lt A
• CASCADE for I in 1 to M generate
• C REP_BLOCK
• port map(REP_IN gt L(I-1),
• 
  REP_OUTgtL(I))
• END GENERATE
• Z lt L(M)
• END Structural

50
Mixed Style RTL Modeling Simple Processor Example
51
Mixed Style Modeling

• ARCHITECTURE architecture_name OF entity_name IS
• Here you can declare signals, constants,
  functions, procedures
• Component declarations
• No variable declarations !!
• BEGIN
• Concurrent statements
• Concurrent simple signal assignment
• Conditional signal assignment
• Selected signal assignment
• Generate statement
• Component instantiation statement
• Process statement
• inside process you can use only sequential
  statements
• END architecture_name

52
Simple Processor
53
Structure of a Typical Digital System
Data Inputs
Control Inputs
Control Signals
Execution Unit (Datapath)
Control Unit (Control)
Data Outputs
Control Outputs
54
Structure of Simple Processor
Data Inputs Data
Control Inputs w, Function
Control Signals
Execution Unit (Datapath)
Control Unit (Control)
R0in..R3in, R0out..R3out, Ain, Gin, Gout,
AddSub, Extern
Data Outputs Bus
Control Outputs Done
55
Processor Instructions
56
Execution Unit
57
N-bit register with enable

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY regn IS
• GENERIC ( N INTEGER 8 )
• PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• En IN STD_LOGIC
• Clock IN STD_LOGIC
• Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
  
• END regn
• ARCHITECTURE Behavior OF regn IS
• BEGIN
• PROCESS
• BEGIN
• IF (Clock'EVENT AND Clock '1) THEN
• IF En '1' THEN
• Q lt D
• END IF

58
N-bit tristate buffer

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY trin IS
• GENERIC ( N INTEGER 8 )
• PORT ( X IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• En IN STD_LOGIC
• Y OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END trin
• ARCHITECTURE Behavior OF trin IS
• BEGIN
• Y lt (OTHERS gt 'Z') WHEN En '0' ELSE X
• END Behavior

59
Packages and component declarations

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE exec_components IS
• COMPONENT regn -- register
• GENERIC ( N INTEGER 8 )
• PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
  
• En IN STD_LOGIC
• Clock IN STD_LOGIC
• Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END COMPONENT
• COMPONENT trin -- tri-state buffers
• GENERIC ( N INTEGER 8 )
• PORT ( X IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
  
• En IN STD_LOGIC
• Y OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END COMPONENT

60
Simple Processor
BusWires
A
R(0)
R(3)
Sum
G
61
Processor Execution Unit (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.exec_components.all
• USE ieee.std_logic_signed.all
• ENTITY Proc_Exec IS
• PORT ( Data IN STD_LOGIC_VECTOR(7 DOWNTO
  0)
• Clock IN STD_LOGIC Rin IN
  STD_LOGIC_VECTOR(0 to 3)
• Rout IN STD_LOGIC_VECTOR(0 to 3)
• Ain IN STD_LOGIC
• Gin IN STD_LOGIC
• Gout IN STD_LOGIC AddSub IN
  STD_LOGIC
• Extern IN STD_LOGIC
• BusWires INOUT STD_LOGIC_VECTOR(7 DOWNTO
  0)
• END Proc_Exec

62
Processor Execution Unit (2)

• ARCHITECTURE Mixed OF Proc_Exec IS
• TYPE RegArray is ARRAY(0 to 3) of
  STD_LOGIC_VECTOR(7 downto 0)
• SIGNAL R RegArray
• SIGNAL A STD_LOGIC_VECTOR(7 DOWNTO 0)
• SIGNAL G STD_LOGIC_VECTOR(7 DOWNTO 0)
• SIGNAL Sum STD_LOGIC_VECTOR(7 DOWNTO 0)

63
Processor Execution Unit (3)

• BEGIN
• G1 FOR i IN 0 TO 3 GENERATE
• Regs regn PORT MAP (
• D gt BusWires,
• En gt Rin(i),
• Clock gt Clock,
• Q gt R(i))
• Trins trin PORT MAP (
• X gt R(i),
• En gt Rout(i),
• Y gt BusWires)
• END GENERATE

64
Processor Execution Unit (4)

• RegA regn PORT MAP (
• D gt BusWires,
• En gt Ain,
• Clock gt Clock,
• Q gt A)
• RegG regn PORT MAP (
• D gt Sum,
• En gt Gin,
• Clock gt Clock,
• Q gt G)
• triG trin PORT MAP (
• X gt G,
• En gt Gout,
• Y gt BusWires)

65
Processor Execution Unit (5)

• ALU WITH AddSub Select
• Sum lt A B WHEN 0,
• A B WHEN OTHERS
• Tri_extern trin PORT MAP (
• X gt Data,
• En gt Extern,
• Y gt BusWires)
• END Mixed

66
Control Unit
67
Processor Instructions
68
Simple Processor
BusWires
A
R(0)
R(3)
Sum
G
69
Counter of instruction clock cycles
T
T
T
T
1
2
3
0
y
y
y
y
0
1
2
3
2-to-4 decoder
w
w
En
0
1
Count
1
Q
Q
1
0
Clock
Up-counter
Clear
Reset
70
The Function Register and Decoders
X
X
X
X
Y
Y
Y
Y
I
I
I
I
0
1
2
3
0
1
2
3
0
1
2
3
y
y
y
y
y
y
y
y
y
y
y
y
0
1
2
3
0
1
2
3
0
1
2
3
2-to-4 decoder
2-to-4 decoder
2-to-4 decoder
w
w
w
w
w
w
En
En
En
0
1
0
1
0
1
1
1
1
Clock
Function Register
FR
in
f
f
Rx
Rx
Ry
Ry
1
0
1
0
1
0
Function
71
Control signals asserted in each operation and
time step
72
Packages and component declarations

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE control_components IS
• COMPONENT dec2to4
• PORT (w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3)
  )
• END COMPONENT
• COMPONENT upcount
• GENERIC ( N INTEGER 2 )
• PORT ( Clock IN STD_LOGIC
• Reset IN STD_LOGIC
• Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
• END COMPONENT
• END control_components

73
N-bit Up Counter (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE ieee.std_logic_unsigned.all
• ENTITY upcount IS
• GENERIC ( N INTEGER 2 )
• PORT (Clock IN STD_LOGIC
• Reset IN STD_LOGIC
• Q BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
  
• END upcount

74
N-bit Up Counter (2)

• ARCHITECTURE Behavior OF upcount IS
• BEGIN
• upcount PROCESS ( Clock )
• BEGIN
• IF (Clock'EVENT AND Clock '1') THEN
• IF Reset '1' THEN
• Q lt (OTHERS gt 0)
• ELSE
• Q lt Q 1
• END IF
• END IF
• END PROCESS
• END Behavior

75
A 2-to-4 binary decoder

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY dec2to4 IS
• PORT ( w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3) )
• END dec2to4
• ARCHITECTURE Dataflow OF dec2to4 IS
• SIGNAL Enw STD_LOGIC_VECTOR(2 DOWNTO 0)
• BEGIN
• Enw lt En w
• WITH Enw SELECT
• y lt "1000" WHEN "100",
• "0100" WHEN "101",
• "0010" WHEN "110",
• "0001" WHEN "111",
• "0000" WHEN OTHERS

76
Processor Control Unit (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.control_components.all
• ENTITY Proc_Control IS
• PORT ( Func IN STD_LOGIC_VECTOR(1 TO 6)
• w IN STD_LOGIC
• Clock IN STD_LOGIC Reset
  IN STD_LOGIC
• Rin OUT STD_LOGIC_VECTOR(0 to 3)
• Rout OUT STD_LOGIC_VECTOR(0 to 3)
• Ain OUT STD_LOGIC
• Gin OUT STD_LOGIC
• Gout OUT STD_LOGIC AddSub OUT
  STD_LOGIC
• Extern OUT STD_LOGIC
• Done OUT STD_LOGIC
• END Proc_Control

77
Processor Control Unit (2)

• ARCHITECTURE Mixed OF Proc_Control IS
• SIGNAL Clear STD_LOGIC
• SIGNAL Count STD_LOGIC_VECTOR(1 DOWNTO 0)
• SIGNAL T STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL FRin STD_LOGIC
• SIGNAL FuncReg IN STD_LOGIC_VECTOR(5 DOWNTO
  0)
• SIGNAL I STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL X STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL Y STD_LOGIC_VECTOR(0 TO 3)
• SIGNAL High STD_LOGIC

78
Counter of instruction clock cycles
T
T
T
T
1
2
3
0
y
y
y
y
0
1
2
3
2-to-4 decoder
w
w
En
0
1
Count
1
Q
Q
1
0
Clock
Up-counter
Clear
Reset
79
Processor Control Unit (3)

• BEGIN
• counter upcount PORT MAP (
• Clock gt Clock,
• Reset gt Clear,
• Q gt Count )
• Clear lt Reset OR Done OR (NOT w AND T(0))
• High lt '1'
• decT dec2to4 PORT MAP (
• w gt Count,
• En gt High,
• y gt T )

80
The Function Register and Decoders
X
X
X
X
Y
Y
Y
Y
I
I
I
I
0
1
2
3
0
1
2
3
0
1
2
3
y
y
y
y
y
y
y
y
y
y
y
y
0
1
2
3
0
1
2
3
0
1
2
3
2-to-4 decoder
2-to-4 decoder
2-to-4 decoder
w
w
w
w
w
w
En
En
En
0
1
0
1
0
1
1
1
1
Clock
Function Register
FR
in
f
f
Rx
Rx
Ry
Ry
1
0
1
0
1
0
Function
81
Processor Control Unit (4)

• functionreg regn GENERIC MAP ( N gt 6 )
• PORT MAP (
• D gt Func,
• En gt FRin,
• Clock gt Clock,
• Q gt FuncReg )
• FRin lt w AND T(0)
• decI dec2to4 PORT MAP (
• w gtFuncReg(5 DOWNTO
  4),
• En gt High,
• y gt I )

82
Processor Control Unit (5)

• decX dec2to4 PORT MAP (
• w gt FuncReg(3
  DOWNTO 2),
• En gt High,
• y gt X )
• decY dec2to4 PORT MAP (
• w gt FuncReg(1
  DOWNTO 0),
• En gt High,
• y gt Y )

83
Control signals asserted in each operation and
time step
84
Processor Control Unit (5)

• control_signals PROCESS (T, I, X, Y)
• BEGIN
• Extern lt '0' Done lt '0' Ain lt '0' Gin
  lt '0'
• Gout lt '0' AddSub lt '0' Rin lt "0000"
  Rout lt "0000"
• CASE T IS
• WHEN 1000 gt null --
  no signals asserted in the time step T0
• WHEN 0100 gt
• CASE I IS
• WHEN 1000" gt -- Load
• Extern lt '1' Rin lt X Done lt '1'
• WHEN "0100" gt -- Move
• Rout lt Y Rin lt X Done lt '1'
• WHEN OTHERS gt -- Add, Sub
• Rout lt X Ain lt '1'
• END CASE
• END PROCESS

85
Processor Control Unit (6)

• WHEN 0010 gt
• CASE I IS
• WHEN 0010" gt -- Add
• Rout lt Y Gin lt '1'
• WHEN 0001" gt -- Sub
• Rout lt Y AddSub lt '1' Gin lt '1'
• WHEN OTHERS gt -- Load, Move
• END CASE
• WHEN OTHERS gt -- define signals asserted in
  time step T3
• CASE I IS
• WHEN 1000" gt -- Load
• WHEN "0100" gt -- Move
• WHEN OTHERS gt -- Add, Sub
• Gout lt '1' Rin lt X Done lt '1'
• END CASE
• END CASE

86
Processor Control Unit (7)

• END PROCESS
• END Mixed