A Reconfigurable FPGABased Readback Signal Generator for HardDrive Read Channel Simulator

1
A Reconfigurable FPGABased Readback Signal
Generator for HardDrive Read Channel Simulator

• Jinghuan Chen Jaekyun Moon Kia Bazargan
• ECE Department
• University of Minnesota

2
Outline

• Problem domain hard disk readback signal
  simulation
• Modeling HDD read
• FPGA implementation
• Hardware platform
• Design components
• Random number generator
• Results and conclusion

Outline
3
Outline

• Problem domain hard disk readback signal
  simulation
• Modeling HDD read
• FPGA implementation
• Hardware platform
• Design components
• Random number generator
• Results and conclusion

Outline
4
Reconfiguration Benefits

• Reuse hardware
• Saves area
• Leaves room for data recovery circuit
• Intermediate data?
• Partial runtime reconfiguration (future work)
• No need to synthesize each configuration(synthesi
  ze individual noise components,assemble at
  runtime)
• Can cover all possible noise combinations
• No need to transfer intermediate data to on-board
  mem

5
Hard Disk Technology

• Disk metal or glass coated with magnetic thin
  film
• Write induce magnetic directions
• Read
• pick up magnetic flux
• Pre-amplification, analog/digital filtering, data
  recovery

V
Readback pulses
Read Process
Write Process
6
Transition Noise

• Trend pack more bits ? more noise
• Transition noise (data dependent)
• Imperfect boundary between bit cells
• ? pulse shifts in time domain
• ? pulse shape deforms

Transition position jitter
Pulse width variation
7
Read / Write Nonlinear Factors

• Head magneto-resistant
• Non-linear in nature different /- amplitude
• Partial erasure
• Irregularity of disk spinning speed
• Head not 100 on the track? cross-talk from
  neighboring track
• Electronics noise

8
Outline

• Problem domain hard disk readback signal
  simulation
• Modeling HDD read
• FPGA implementation
• Hardware platform
• Design components
• Random number generator
• Results and conclusion

Outline
9
Simulating HDD Read / Write Why?

• High demand for reliability
• Very low bit error rate (BER) ? long simulation
• Desktop 10 out of 1013.
• Server 10 out of 1015.
• High throughput
• Push data recovery techniques to the limits
• Need to understand effects of
• Advanced, novel signal processing techniques
• Encoding schemes(e.g., turbo codes, low density
  parity check)
• Hard disk noise diff from other comm systems
• Make dedicated signal generator for simulation
• Previous work software simulation takes DAYS

10
Benefits of Modeling in FPGA

• Speed
• Instead of days, hours
• Hardware integration into data recovery model
• Reconfiguration
• Ability to add/remove different noise components
• Ability to tune parameters of a particular noise
  factor
• Runtime reconfiguration
• Done by time-multiplexing different
  configurationson FPGA
• Pre-synthesized modules
• Possible partial runtime reconfiguration
• Example neighboring track interference might
  bevary among different tracks

11
Modeling Noise Factors

• Inter-symbol interference (neighboring bits)

12
Modeling Noise Factors (cont.)

• Head non-linearity F(x)
• Amplitude loss due to partial erasure

• Disk spinning irregularities
• Modeled as a slow-paced random-walk
• Inter-track interference
• Weighted sum of two uncorrelated signal
  generators(each representing a track)
• Electronics noise
• Additive white bandlimited gaussian noise (AWGN)

13
Outline

• Problem domain hard disk readback signal
  simulation
• Modeling HDD read
• FPGA implementation
• Hardware platform
• Design components
• Random number generator
• Results and conclusion

Outline
14
FPGA Hardware Platform

• FPGA board
• Annapolis Micro Systems FireBird board
• Xilinx XCV1000E FPGA
• 18MB of RAM
• PCI bus interface

MEM
MEM
MEM
XCV1000E
Host Computer
PCI Controller
MEM
MEM
15
Outline

• Problem domain hard disk readback signal
  simulation
• Modeling HDD read
• FPGA implementation
• Hardware platform
• Design components
• Random number generator
• Results and conclusion

Outline
16
Design Hierarchy and Behavior
Board
FPGA
PCI Bus
HOST CPU
On-board RAM
17
Design Behavior

• Restructuring
• FPGA configuration (add / remove noise
  components)
• Model different hard disks
• Initialization / Re-initialization
• Lookup table initializations (change parameters)
• Pulse lookup tables
• Gaussian conversion tables
• Multiplier lookup tables

18
Signal Generator Components
Input

• Data / interfering track
• Data main data track
• Interfering neighboring track
• Both pipelined
• Independent random number generators
• Weighted sum to model interference

19
Data Track Components
Data Track
LHCAPRNG
NLTS
WERR
20
Outline

• Problem domain hard disk readback signal
  simulation
• Modeling HDD read
• FPGA implementation
• Hardware platform
• Design components
• Random number generator
• Results and conclusion

Outline
21
Uniform Random Number Generation

• Classic method LFSR (Linear Feedback Shift Reg)
• Large area
• Feedback loop makes routing hard
• Linear hybrid cellular automata (LHCA)
• Smaller in area ( factor of 5 reduction)
• Needs a number of initialization cycles
• Null boundary ? no feedback loop
• Not every bit position random? use one bit per n
  registers
• Implementation use Rule 90 and Rule 150 to
  combine neighboring bits

22
LHCA Implementation

• Rule 90

1
i-1
i
N
I1
0
0

• For each bit position, carefully chooseRule 90
  or Rule 150

23
Example Modeling WERR

• WERR caused by irregular disk spinning speed
• Modeled as a slow-paced random walk
• Add one write error in every NWERR clock cycles

(1,-1)
RNG
1
ò
0
0
CLK k.NWERR(k1,2,3, ...)
24
Non-uniform Random Number

• Use a uniform RNG, lookup the values
  ofnon-uniform random numbers from a table
• Lookup table
• User-defined (Gaussian, etc.)
• Cumulative distribution function (CDM)
• Encoder
• Round-off to L bits (quantization error depends
  on L)

25
Example Gaussian PDF
26
Outline

• Problem domain hard disk readback signal
  simulation
• Modeling HDD read
• FPGA implementation
• Hardware platform
• Design components
• Random number generator
• Results and conclusion

Outline
27
Sample Output
1.0
0.5
0.0
-0.5
-1.0
0
200
400
600
800
1000
28
Resource Utilization and Speedup

• Configuration 0 uses 99 of chip area
• Clock speed 70 MHz
• Speedup compared to software 4 hr vs. 50,000 hr

29
Floorplan
30
Floorplan
31
Reconfiguration Benefits

• Reuse hardware
• Saves area
• Leaves room for data recovery circuit
• Intermediate data?
• Partial runtime reconfiguration (future work)
• No need to synthesize each configuration(synthesi
  ze individual noise components,assemble at
  runtime)
• Can cover all possible noise combinations
• No need to transfer intermediate data to on-board
  mem
• Implementation
• Constrain the floorplan
• Use JBits

32
Constrained Floorplan for Partial Reconfiguration
33
Placement for Partial Reconfig.