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Analog Digital VLSI Design Lecture 3 layout, design rules, mismatch

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Large device= many small unit devices. Same boundary ... metal1. metal2. Compute w/L? CIRCUIT AND LAYOUT. Try more examples. CAPACITORS. CAPACITOR LAYOUTS ... – PowerPoint PPT presentation

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Title: Analog Digital VLSI Design Lecture 3 layout, design rules, mismatch


1
Analog Digital VLSI DesignLecture 3layout,
design rules, mismatch
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CMOS LAYOUTS
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MOS LAYOUT
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2?
2?
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5?
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Junction cap-single transistor
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How to reduce parasitic capacitances?
  • Careful layout by junction sharing

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6?
20?
6?
6?
5?
5?
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Fingered layout
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View of fingered layout
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Matching Issues
  • Large devicegt many small unit devices
  • Same boundary conditions for devices

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Unit components
  • (W/L)1 20, (W/L)2 80, ratio 4
  • We take unit device (W/L)u 10
  • After fab (W/L)u ? 8
  • (W/L)2 8(W/L)u
  • (W/L)1 2(W/L)u
  • Thus, ratio remains same, if same unit device is
    used

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What if unit device changes?
Since one device is facing larger change in
dimension, maintaining constant ratio would be
difficult. We should have same change in all
unit devices
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Reduce mismatches
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D
D
D
S
S
S
S
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Bulk (backgate contact)
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Other layouts of MOS
Annular transistor
Elongated annular transistor
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Dense MOS layouts
metal1
metal2
Bent transistor
Waffle transistor
Compute w/L?
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CIRCUIT AND LAYOUT
Try more examples
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CAPACITORS
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CAPACITOR LAYOUTS
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Over-Etching
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  • Let
  • C1/ C2 3.4 21.4
  • 6/2 1.4/1
  • 6/2---can be implemented by using unit
    capacitors
  • 1.4/1---we require non unit capacitor
  • Mismatch can occur due to second term

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No mismatch condition
  • We should design non unit cap. Such that ratio
    (1.4) remains constant even after overetching
  • How to design?
  • What is the condition?

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Condition
c1 c2
er1 er2
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Non unit sized cap
1.4
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RESISTOR LAYOUT
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Big Resistor
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BIG RESISTOR
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