Team M1 Enigma Machine Milestone 11 - 24 April, 2006

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Team M1Enigma MachineMilestone 11 - 24
April, 2006

• Adithya Attawar (M11)
• Shilpi Chakrabarti (M12)
• Mike Sokolsky (M14)
• Design Manager Prateek Goenka

Design Manager Prateek Goenka
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Status
STATUS

• Finished
• Behavioral Verilog and C simulation
• Structural Verilog
• Logic optimization
• Module-level spice delay and power simulations
• Floorplan
• Top-level schematic testing
• Functional block layout
• Simulation of functional blocks
• Global Layout
• To do
• Global Simulation

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Final Floorplan
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Poly Layer Mask
Density8.25
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Metal1 Layer Mask
Density31.36
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Metal2 Layer Mask
Density 16.96
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Metal3 Layer Mask
Density 12.25
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Metal4 Layer Mask
Density 11.44
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Ram Delay in Schematic
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Ram Delay in ExtractedRC
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FSM Delay in Schematic
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FSM Delay in ExtractedRC
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Propagation Delay
Module Schematic ExtractedRC
RAM 850p 1.154n
ROM 1.2n
Adder 828p 1.017n
FSM 362p 412p
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Design specifications
Module Transistor count Area Transistor Density Aspect Ratio
Muxes 270 748 0.36 0.05,0.14
RAM 1462 6,507 0.23 0.39
Adder 298 1404 0.21 0.40
ROM 2126 10,702 0.20 0.27
Counters 2746 10,434 0.26 0.26
Registers 1904 7,533 0.25 1.63,2.64
FSM 441 1,627 0.27 2.29
Total 9247 49,581 0.19 0.79
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Questions?