Introduction to CMOS VLSI Design Lecture 11: Sequential Circuits

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Introduction toCMOS VLSIDesignLecture 11
Sequential Circuits

• David M. Zar
• Washington University in St. Louis
• Based on original work, with permission, by
• David Harris
• Harvey Mudd College

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Outline

• Sequencing
• Sequencing Element Design
• Max and Min-Delay
• Clock Skew
• Time Borrowing
• Two-Phase Clocking

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Sequencing

• Combinational logic
• output depends on current inputs
• Sequential logic
• output depends on current and previous inputs
• Requires separating previous, current, future
• Called state or tokens
• Ex FSM, pipeline

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Sequencing Cont.

• If tokens moved through pipeline at constant
  speed, no sequencing elements would be necessary
• Ex fiber-optic cable
• Light pulses (tokens) are sent down cable
• Next pulse sent before first reaches end of cable
• No need for hardware to separate pulses
• But dispersion sets min time between pulses
• This is called wave pipelining in circuits
• In most circuits, dispersion is high
• Delay fast tokens so they dont catch slow ones.

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Sequencing Overhead

• Use flip-flops to delay fast tokens so they move
  through exactly one stage each cycle.
• Inevitably adds some delay to the slow tokens
• Makes circuit slower than just the logic delay
• Called sequencing overhead
• Some people call this clocking overhead
• But it applies to asynchronous circuits too
• Inevitable side effect of maintaining sequence

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Sequencing Elements

• Latch Level sensitive
• a.k.a. transparent latch, D latch
• Flip-flop edge triggered
• a.k.a. master-slave flip-flop, D flip-flop, D
  register
• Timing Diagrams
• Transparent
• Opaque
• Edge-trigger

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Sequencing Elements

• Latch Level sensitive
• a.k.a. transparent latch, D latch
• Flip-flop edge triggered
• a.k.a. master-slave flip-flop, D flip-flop, D
  register
• Timing Diagrams
• Transparent
• Opaque
• Edge-trigger

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Latch Design

• Pass Transistor Latch
• Pros
• Cons

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Latch Design

• Pass Transistor Latch
• Pros
• Tiny
• Low clock load
• Cons
• Vt drop
• Non-restoring
• Back-driving
• output noise sensitivity
• dynamic
• diffusion input

Used in 1970s
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Latch Design

• Transmission gate
• -

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Latch Design

• Transmission gate
• No Vt drop
• Requires inverted clock
• Non-restoring
• Back-driving
• output noise sensitivity
• diffusion input

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Latch Design

• Inverting buffer
• Fixes either

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Latch Design

• Inverting buffer
• Restoring
• No back-driving
• Fixes either
• Output noise sensitivity
• Or diffusion input
• Inverted output
• Still dynamic

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Latch Design

• Tristate feedback

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Latch Design

• Tristate feedback
• Static
• Back-driving risk
• Static latches are now essential

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Latch Design

• Buffered input

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Latch Design

• Buffered input
• Fixes diffusion input
• Noninverting
• No back-driving
• Static
• Output load affects feedback time

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Latch Design

• Buffered output

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Latch Design

• Buffered output
• No back-driving
• Load doesnt slow down feedback path
• Widely used in standard cells
• Very robust (most important)
• Rather large
• Rather slow (1.5 2 FO4 delays)
• High clock loading

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Latch Design

• Datapath latch
• -

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Latch Design

• Datapath latch
• Smaller, faster
• unbuffered input
• (back-driving when switching)

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Flip-Flop Design

• Flip-flop is built as pair of back-to-back latches

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Enable

• Enable ignore clock when en 0
• Mux increase latch D-Q delay
• Clock Gating increase en setup time, skew

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Reset

• Force output low when reset asserted
• Synchronous vs. asynchronous

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Set / Reset

• Set forces output high when enabled
• Flip-flop with asynchronous set and reset

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Sequencing Methods

• Flip-flops
• 2-Phase Latches
• Pulsed Latches

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Timing Diagrams
Contamination and Propagation Delays
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Max-Delay Flip-Flops
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Max-Delay Flip-Flops
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Max Delay 2-Phase Latches
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Max Delay 2-Phase Latches
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Max Delay Pulsed Latches
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Max Delay Pulsed Latches
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Min-Delay Flip-Flops
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Min-Delay Flip-Flops
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Min-Delay 2-Phase Latches
Hold time reduced by nonoverlap Paradox hold
applies twice each cycle, vs. only once for
flops. But a flop is made of two latches!
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Min-Delay 2-Phase Latches
Hold time reduced by nonoverlap Paradox hold
applies twice each cycle, vs. only once for
flops. But a flop is made of two latches!
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Min-Delay Pulsed Latches
Hold time increased by pulse width
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Min-Delay Pulsed Latches
Hold time increased by pulse width
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Time Borrowing

• In a flop-based system
• Data launches on one rising edge
• Must setup before next rising edge
• If it arrives late, system fails
• If it arrives early, time is wasted
• Flops have hard edges
• In a latch-based system
• Data can pass through latch while transparent
• Long cycle of logic can borrow time into next
• As long as each loop completes in one cycle

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Time Borrowing Example
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How Much Borrowing?
2-Phase Latches
Pulsed Latches
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Clock Skew

• We have assumed zero clock skew
• Clocks really have uncertainty in arrival time
• Decreases maximum propagation delay
• Increases minimum contamination delay
• Decreases time borrowing

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Skew Flip-Flops
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Skew Latches
2-Phase Latches
Pulsed Latches
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Two-Phase Clocking

• If setup times are violated, reduce clock speed
• If hold times are violated, chip fails at any
  speed
• In this class, working chips are most important
• No tools to analyze clock skew
• An easy way to guarantee hold times is to use
  2-phase latches with big nonoverlap times
• Call these clocks f1, f2 (ph1, ph2)

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Safe Flip-Flop

• In class, use flip-flop with nonoverlapping
  clocks
• Very slow nonoverlap adds to setup time
• But no hold times
• In industry, use a better timing analyzer
• Add buffers to slow signals if hold time is at
  risk

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Summary

• Flip-Flops
• Very easy to use, supported by all tools
• 2-Phase Transparent Latches
• Lots of skew tolerance and time borrowing
• Pulsed Latches
• Fast, some skew tol borrow, hold time risk

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Metastability

• Latches (flops) are bistable devices.
• Depending on inputs, output is 0 or 1 and is
  stable.
• If inputs are just right, the output can be at
  ½.
• METASTABILITY
• Resolution time is unknown due to noise, not due
  to metastability being random.
• Metastability will always occur with these inputs.

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Metastable State
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Metastable State in Dynamic Latch