Lesson 4:

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Lesson 4 Just like LEGO

• The NAND gate
• Reading CMOS gates
• Designing CMOS gates

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Logic
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NAND 2-inputs
Gates areinverters in disguise!
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NAND 3-inputs
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NAND 3-inputs
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NAND Switching Time, Propagation Delay

• tLow2High Rp/N (NCout,pCout,n/NCload)
• tHigh2Low NRn (Cout,n/NNCout,pCload)
• Gate Delay1/2(tL2H tH2L)
• n,p n-channel, p-channel transistors.
• Rp,Rn Ron of respective transistors.
• N number of Inputs.

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Estimation of Gate Delay
Gate Delay K1(pSec) K2 (pSecum/fF) Cload /
WnWnWidth of n-channel FET (Wp/Wnconstant)K1
K2 determined from spice simulation of cascaded
inverters. Wp/Wn K1 K2 1 39 12.8 2 38 8.78
3 41 6.35 When FETs in series, the effective W
is respectively smaller. Cload calculated from
Fan-out Capacity(per Gate) Capacity of Line.
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NAND 3-inputs
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NAND 3-inputs
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Reading CMOS gates
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Designing CMOS gates
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Complex CMOS gates

• Can a compound gate be arbitrarily complex?
• NO, propagation delay is a strong function of
  fan-in
• FO ? Fan-out, number of loads connected to the
  gate
• 2 gate capacitances per FO interconnect
• FI ? Fan-in, Number of inputs in the gate
• Quadratic dependency on FI due to
• Resistance increase
• Capacitance increase
• Avoid large FI gates (Typically FI ? 4)

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NAND Switching PointVSP(bn /
(Nbp))1/2VT,n(VDD-VT,p)
--------------------------------------1(bn /
(Nbp))1/2 N number of Inputs.n,p
n-channel, p-channel transistors.