Analog to Digital Converters

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Analog to Digital Converters

• Josh Peabody
• Chris Cox
• Alejandro Jaramillo
• 10/04/01

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Analog to Digital ConvertersPresentation Outline

• Definition
• Applications
• Conversion Process
• Converter Types
• A/D Converter Comparison
• HC11 A/D Process
• HC11 A/D Process Examples

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A/D Conversion Definition

• Converting analog signals into binary words

Clock signal
Input
A/D Conversion
Output
Sample and hold
analog signal segment
digital signal
analog signal
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A/D Converters Applications

• Strain Gages
• Thermocouples
• Data Acquisition Devices
• Load Cells
• Microphones (voice circuitry)
• Process and Store

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A/D Conversion Process

• Sampling
• Encoding

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A/D Conversion Process

• Sampling
• Sampling Rate (determines x-axis increments)
• Frequency with which the A/D converter checks
  the analog signal.
• Rule of Thumb Minimum sampling rate should be
  at least twice the highest data frequency of the
  analog signal (a.k.a Aliasing).
• Resolution
• Accuracy

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A/D Conversion Process

• Sampling

Resolution
Clock Signal
Output Quantization Level
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A/D Conversion Process

• Sampling
• Resolution (determines y-axis increments)
• Smallest change in output that will result in a
  change in the digital input.
• Resolution VFS/2n
• VFS assumes analog input in volts.
• n number of bits in digital output.
• 2n number of states.

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A/D Conversion Process

• Accuracy (Accuracy increases as n increases.)
• Increased accuracy results with greater
  resolution (y-axis divisions) and higher sampling
  rate (x-divisions).
• Low Accuracy Improved Accuracy

Resolution
Resolution
Time
Time
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A/D Conversion Process

• Encoding
• Assigning a unique digital code to each sample.
• Matching the digital code to the input signal.

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A/D Conversion Process

• Example 3-Bit A/D Input-Output

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A/D Converter Types

• Converters
• Successive-Approximation (Sampling) Converter
• Dual-Slope Converter
• Voltage-to-frequency (V/F) Counting Converter
• Sigma-Delta Converter
• RC Converter
• Pulse-width modulation (PWM) Converter

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A/D Converter Types

• Converters
• Successive-Approximation (Sampling) Converter
• Guess the answer, use a D/A to convert it to an
  analog voltage and compare it to the voltage
  being measured adjust your guess accordingly
• Capable of high speed. Reliable.
• Similar to the ordering weighing (on a scale) of
  an unknown quantity on a precision balance, using
  a set of weights, such as 1g, 0.5g, 0.25g, etc.

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A/D Converter Types

• Successive-Approximation Converter
  3-bit example

Comparator
3.7V
VIN
Control Logic
H
L
H
H

-
3.75
3.13V
3.13V
2.50V
SetBit
ClrBit
Result
1 0 0
1 0 0 0
1 0 1 0
1 0 1
1 0 0
1 0 1
Digital toAnalog Converter
VREFH
VREFL
Digital Output
Black UntestedRed TestingBlue Confirmed
5V
0V
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A/D Converter Types

• Example Problem
• You are given a successive approximation ADC
  (3-bit resolution or 0.625 Volts of the Vref).
  You are told that Vin3.7Volts and
  Vref5Volts. Find the digital value of Vin.
• Solution Divide Vref by 2. Compare Vref/2 with
  Vin. If Vin is greater, turn MSB ON. If Vin is
  less than Vref/2, turn MSB off.
• Calculate the state of MSB
• Compare Vin3.7 Volts and VVref/22.5Volts.
  
• Since 3.7 gt 2.5 Þ MSB 1 (turned on)
• Calculate the state of MSB-1
• Compare Vin3.7 Volts and V(Vref/2
  Vref/4)(2.51.3)3.8 Volts.
• Since 3.7 lt 3.8 Þ MSB-1 0 (turned off)

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A/D Converter Types

• Example Problem (cont)
• Calculate the state of MSB-2
• Go back to the last voltage value that caused it
  to be turned on (in this case 2.5Volts) and
  add Vref/8 to it and compare with Vin.
• Compare Vin and (2.5 (Vref/8)3.13)
• Since 3.7 gt 3.1 Þ MSB-2 1 (turned on)

Digital Results
MSB-1
MSB-2
MSB
0
1
1
ResultsVfs(digital results10/n) Results5Volts
(5/8) 3.13 Volts
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A/D Converter Types

• Converters
• Successive-Approximation (Sampling) Converter
• Conversion time is clock rate times number of
  bits.
• Example with 8-bit, 2-MHz clock rate
• Conversion time (clock period) x (bits being
  converted)
• Conversion time (0.5 micro-sec) x (8-bits) 4
  microsec

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A/D Converter Types

• Converters
• Dual-Slope Converter
• Counts a succession of clock pulses whose number
  depends on the amplitude of a signal integrated
  within an integrator.
• Conversion time is two clock periods times the
  number of quantitization levels.
• Example with 8-bit, 2-MHz clock rate
• Conversion time2 x (clock period) x
  (quantitization levels)
• Conversion time2 x (0.5 micro-sec) x (256) .256
  msec
• Longer than Successive-Approximation, but
  cheaper.

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A/D Converter Comparison
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A/D Conversion with the HC11
Where to look

• Chapter 12 in Reference Manual
• Chapter 10 in Technical Data Text
• Pg. 40-41, 49 in Reference Guide

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A/D Conversion with the HC11

• 8 channel/bit input
• VRL 0 volts
• VRH 5 volts
• Digital input on PE

CCF
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A/D Conversion with the HC11
Some additional notes

• 0V lt analog input lt 5V
• Charge pump allows VRH max 6-7V
• VRL and VRH convert to 00 and FF
• Digital input of Port E pins not recommended
  during A/D sample time

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A/D Conversion with the HC11
Whats the magic in the chip?
HC11 Contains DAC, comparator, and SAR
DAC samples and holds input, then compares
voltage to comparator
Result of comparison stored in SAR. When sequence
is complete, the contents are dumped to
appropriate result register
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A/D Conversion with the HC11
Conversion Sequence
Sample (12)
Bit 7 (4)
6 (2)
_ (2)
0 (2)
End (2)
ADCTL write (1)
Successive approximation
1st, ADR1
2nd, ADR2
3rd, ADR3
4th, ADR4
CCF
0
32
64
96
128 total
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A/D Conversion with the HC11

• ADR ¼ of result registers SAR feeds. ADR
  behavior is governed by the ADCTL.
• CCF is the conversion complete flag, indicating
  the end of the A/D process.
• Internal RC oscillator may substitute for system
  E clock

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A/D Conversion with the HC11
Options Register (1039)
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A/D Conversion with the HC11
ADPU 0 power down 1 power up
CSEL 0 A/D and EEPROM use E clock 1 A/D and
EEPROM use internal RC
DLY 0 No delay is used and MCU resumes within
approx. 4 cycles. 1 4000 E clock cycle delay
imposed to allow crystal stabilization
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A/D Conversion with the HC11
ADCTL register (1030)
CCF Conversion Complete flag note read
only! Bit 6 not implemented SCAN Continuous
Scan MULT Controls number of channels
CD CA Channel control See pg. 40 of
Reference Guide
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A/D Conversion with the HC11
ADR Behavior
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A/D Conversion with the HC11
A/D Result Registers (ADR1 ADR4)
ADR1 1031 ADR2 1032 ADR3 1033 ADR4
1034
Note All registers are read only accessible
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A/D result registers

• Eight inputs on Port E
• AN0 (PE0) through AN7 (PE7)

• Four result registers
• ADR1 - ADR4, at 1031 - 1034
• Can be configured to be either
• Inputs PE0-PE3
• Inputs PE4-PE7
• A single input, sampled four times in a row

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A/D Control Registers
CB
CA
SCAN
MULT
CD
CC
CCF
ADCTL (1030)
0
Reset to 0 0 u u u u u u
MULT - Single or multiple channel 0 Sample a
single channel (four times) 1 Sample four
channels
CD,CC,CB,CA - Channel selection If MULT is 0,
then CC-CA bits specify the channel If MULT is
1, then CC specifies the group 0 Sample
AN0-AN3, 1 Sample AN4-AN7 CD is reserved for
factory test use
CCF - Conversion Complete Flag Set when all four
conversions are complete Cleared by writing to
ADCTL - starts the next conversion
SCAN - Continuous scan mode 0 Take one set of
four conversions and stop 1 Continually perform
new conversions
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A/D Options
CSEL
0
ADPU
CR1
CR2
OPTION (1039)
IREQ
DLY
CME
Reset to 0 0 u u u u u u
ADPU - A/D Charge Pump 0 Turn off the A/D 1
Turn on the A/D (by enabling the charge
pump) Note Wait at least 100 microseconds
before using the A/D (This is 200 cycles at a
2MHz E-clock)
CSEL - A/D Clock select 0 Use the E-clock for
the A/D 1 Use a special internal A/D clock that
runs at around 2MHz Note If the E-clock is
750KHz or higher, CSEL should be 0. Otherwise
CSEL should be 1.
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Using the HC11 A/D to Read Chan. AN0
ADPU
CR1
CR2
OPTION (1039)
CSEL
IREQ
DLY
CME
0
CCF
CB
CA
ADCTL (1030)
0
SCAN
MULT
CD
CC
OPTION EQU 1039ADCTL EQU 1030ADR1 EQU 1031AD
RESULT RMB 1
Turn on charge pump and select clock source
ORG 2000 LDAA 80 ADPU1,CSEL0 STAA OPTION

Delay for charge pump to stabilize
LDY 30 delay for 105 ms DELAY DEY BNE DELAY
Set ADCTL to start conversion
LDAA 10 SCAN0,MULT1,CHAN GRP00 STAA ADCTL
start conversion
LDX ADCTL check for complete flag BRCLR 0,X
80 CCF is bit 7
Wait until conv. complete
LDAA ADR1 read chan. 0 STAA ADRESULT store in
result SWI
Read result
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Analog Input translation Table
(1) of VRH-VRL, (2) VRH5 VRL0, (3) VRH3.3
VRL0
Page 41 of the programming reference guide
(Pocket book)
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Example
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A/D Converter Presentation References

• Hnatek, Eugene R. A users handbook of D/A and
  A/D converters. John Wiley Sons, Inc., 1976.
• Bolton, W. Mechatronics Electonic Control
  Systems in Mechanical and Electrical
  Engineering. Addison Wesley Longman Limited.
  1999.
• http//www.mil.ufl.edu/4744/software.html
• http//paul.spu.edu/bolding/ee3280/3280resources.
  html
• Chapter 12 in Reference Manual
• Chapter 10 in Technical Data Text
• Pg. 40-41, 49 in Reference Guide

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FIN
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