G. Drake Electronics for Next-Generation Telescopes Oct. 21, 2005 p. 1

1
(No Transcript)
2
Instrumentation Concepts

• The Nature of Events

• Present Photo-Detectors are Typically
  Single-Anode PMTs
• Telescope Mirrors Focus Light onto Photo-Cathodes
• PMT Signals are Digitized (8-12 Bits) using FADCs
• Veritas 500 MHz FADC Provides 2 nS Timing

• Digital Calorimetry

Veritas Telescope 1 Images Courtesy of Liz Hayes
Veritas
3
Instrumentation Concepts

• Photo-Detectors for Next Generation Telescopes

• It is Desirable to Increase the Angular
  Resolution of the Images
• Measure Lower Energies
• Reduce Background
• Implies
• Smaller Pixels 0.15 ? lt
  0.05
• More Channels for Same FOV
  500 - 1000 ? 10,000
• The Technology is Here Now, and Continues to
  Advance
• Multi-Anode PMTs
• Multi-Channel Plates
• Silicon PMTs
• APDs

Hamamatsu H8500 64 anode PMT
Pixel (5.8mm)2
Burle Planacon Micro-Channel Plate
85011-501 64 anode
PMT Pixel (6mm)2

• Common in HEP, Need RD for Future Telescopes

4
Instrumentation Concepts

• Photo-Detectors for Next Generation Telescopes

Teststand at Argonne
5
Instrumentation Concepts

• Photo-Detectors for Next Generation Telescopes

• High-Density Photo-Detectors
• Will Require High-Density
• Electronics
• More Circuitry per Unit Volume
• Short Connections to Detector to Enhance
  Performance
• Level 0 Triggering -
  Zero-Suppress at Front End
• Data Stream Out to Back-End
• Need Low Power
• High Channel Count

The Present
Front-End Electronic Packaging for HESS

• Circuitry On-Board Photo-Detector

The Future
Front-End Electronics Mounted on Base

• Need for Custom Integrated Circuit

6
Instrumentation Concepts

• Application-Specific Integrated Circuits
  (ASICs)

• Mature Technology
• ASICs Have Been Around Since Mid-1980s
• 7 micron ? 0.12 micron
• CMOS, Mixed Bipolar/CMOS,
  Silicon Germanium, Gallium Arsenide
• Multi-Project Submission Services Cater to
  Teaching Prototyping ? MOSIS
• Foundries Cater to Production

• Relatively Inexpensive

7
Instrumentation Concepts

• The Pros Cons of Using an ASIC

• The Pros
• High-Performance Circuitry
• Small Size
• Low Power
• Inexpensive for Large Quantity
  Production
• The Cons
• Long Learning Curve for Tools
• High Cost of Tools (0 for Educational
  Institutions)
• Development Time 1-2 yrs.
• Need Special Test Facilities
• Cost-Effective Only for Very Small Quantities
  (Prototype) or Very Large Quantities

Photo of DCAL ASIC for Linear Collider
Courtesy of Ray Yarema, Fermilab

• Telescope Instrumentation Project
• is in On-Par with
• Large HEP Experiments,
• Where ASICs are Used Routinely

• Significant Capital Investment

8
Instrumentation Concepts

• ASIC Functionality?

• Traditional Pulse-Height Digitization
• Good Pulse-Height Resolution
• Complex Circuitry
• High-Speed High Power
• Lots of Bits to Read Out
• Difficult to Trigger
• Correction Overheads Pedestals, Calibrations,
  Linearity

• A New Idea Digital Imaging / Photon
  Discrimination (Swordy)
• Assume Small Pixel Size (Required)
• Most of Time, Single pes Will Hit Individual
  Pixels, True For Signal,
  Noise, and Background
• Instrumentation Each Pixel Has A Discriminator,
  Efficient at 1 pe

9
Instrumentation Concepts

• A New Concept Digital Imaging

Pulse-Height Temperature Plot
Hit Map
(Artists Conception)
10
Instrumentation Concepts

• A New Concept Digital Imaging (Cont.)

Low Energy Signals
Pulse-Height Temperature Plot
Hit Map
(Artists Conception)
11
Instrumentation Concepts

• A New Concept Digital Imaging (Cont.)

Noise (Dark Current NSB) Rejected by Level 0
Trigger
(Artists Conception)
12
Instrumentation Concepts

• A New Concept Digital Imaging (Cont.)

• Strengths in Approach
• Greatly Reduced Background per Pixel
• Very Simple Electronics
• Greatly Reduces Data Volume
• Relatively Easy to Trigger

• Difficulties, Additional Thoughts, Ideas,
  Studies
• Shape of Hit Pattern as a Function of Energy?
• Time Over Threshold for Crude Pulse Height?
• Fold in View from Multiple Telescopes (Yes)
• Pulse Height Digitization of Dynode?
• Use of Out-Riggers for Pulse Height Measurement?
• Issues with QE, Gain Uniformity, Single pe
  Response

• Simulations Studies in Progress

13
Instrumentation Concepts

• Basic System Requirements Design Choices

• Nature of Data Timestamp Hit Pattern (Chip ID
  Appended Later)
• Timing Resolution 1-2 nS
• Raw Data Rate 1 - 10 MHz per Pixel
• Overall Output Data Rate 1-10 KHz (After
  L0/L1 Trig)
• Live Time 100 (_at_ Max Event Rate)
• Triggering
• Level 0 1. More Than 1 Pixel Hit in a Time
  Window
• 2. Geometrical Constraints
• Level 1 Trigger from Neighboring
  Photo-Detectors
• Data Output High-Speed Serial Link, Possibly
  Fiber
• Event Selection Filtering High-Level
  Triggering in Back-End,
• Using
  Timestamps and Geometrical Mapping

14
Conceptual Design of ASIC

• Front-End ASIC

• Front End Amplifier Discriminator Senses Hits
  Above Threshold
• 30-Bit Timestamp Counter Runs at 500 MHz
• Comparator States Clocked into Shift Register -
  Buffer for Trigger Decision, 1000 Stages (2 usec)
• Save States Timestamp on Ext. Trig. or
  Self-Trigger
• Counters Reset Once per Sec, Synchronously Across
  System
• Serial Data Output 100 Mbit/sec, 94
  Bits/Event, 1 uSec/Event
• Serial I/O Separate Data, Control, Trigger
• Services 64 CH

15
Conceptual Design of ASIC

• Front-End ASIC (Cont.)

• Similar in Concept to Chip Development in
  Progress for Linear Collider ? DCAL
• Collaboration with FNAL ASIC Design Group
• Design Work Being Done by Abder Mekkaoui Jim
  Hoff

• New Chip Must be Faster
• 0.13 micron SiGe

16
Conceptual Design of ASIC

• Front-End ASIC (Cont.)

Draft

• Discussions with FNAL ? They are Interested!
• Work in Progress on Establishing Another
  Collaboration with FNAL ASIC Design Group
• Design Work Could Begin in 2006
• First Stage Develop Models, Sims, Basic Design
• Proof-of-Principle for 2nd Stage Funding

17
Summary

• Photo-Detector Technology is Advancing,
• From Which Future Telescopes Can Benefit
• New Telescopes Will Need Smaller Pixels,
• Higher Level of Electronics Integration
• Custom ASICs Are Common Now in
  
• High-Performance Instrumentation
• Preliminary Design Work RD to Begin Soon
• Leverages Resources of National Labs

• High-Level Integration, High Channel Count, Low
  Power