The outcome

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FPGA Based Engine Feedback Control AlgorithmsA
Virtual Heat Release sensor
The outcome
Carl Wilhelmsson PhD Student, Control
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Conclusions

• It is possible to implement an internal
  combustion analysis related algorithm in an
  ASIC/FPGA environment.
• Disregarding the synchronous thinking between the
  engine and FPGA board enables very low latencies
  without any major drawback.
• Extraordinary performance can be achieved using
  the described system
• A sample of Pcyl is processed and corresponding
  Qhr is calculated before any engine can move 0.02
  CAD
• 50 MHz FPGA throughput (AD converter slowing
  down) ? 12 complete (1205 Sample) HR analysis
  / CAD _at_ 1200rpm

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FPGA Based Engine Feedback Control AlgorithmsA
Virtual Heat Release sensor

• Background
• Algorithm
• Experimental setup
• Results
• Conclusions
• Publications
• FPGA Continuation

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Background
Low temperature combustion

• As you all know the HCCI engine, and derivates
  are good options for reducing pollutants
• The drawback shared by the HCCI concepts are
• High emissions of HC
• The lack of a direct combustion phasing actuator
• Limited load range

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Closed loop HCCI control
Background

• Much effort spent to achieve feedback control of
  the HCCI engine with the help of different
  actuators
• HR algorithm needed in a Closed Loop Combustion
  Control system
• Total amount of energy released
• Combustion phasing
• Combustion duration

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Limited resources
Background

• HR algorithm not easily implemented in a limited
  capacity system
• Current direction of feedback systems appear to
  be more and more complex controllers including
  model based controllers, for example MPC

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New technology
Background

• An FPGA is a reconfigurable ASIC
• Using FPGA it is possible to realise small series
  of fully customized hardware
• The usage of an FPGA gives the possibility of
  very high throughput together with low delay time
  and low jitter
• Technology already proven in a wide variety of HD
  applications
• Scientific simulations
• Batch computing
• Real time image analysis
• Real time signal processing

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Related FPGA-feedback control
Background

• Wei et al. 10 Implemented and evaluated
  different PID architectures in a FPGA environment
• He and Ling 11 implemented an MPC controller in
  an FPGA and evaluated this in a HILS system on a
  matlab based aircraft model

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Setup schematics
Experimental setup
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FPGA Hardware
Experimental setup

• Xilinx Virtex 4 FPGA, 24200 logic cells 168Kb
  ram, 100MHz clock
• Memec Virtex4 LC prototype board (www.memec.com)
• Expansion header for prototype analog design
• Ethernet, RS232, 2x20 LDC display etc
• Memec P160 Analog expansion card
• Dual 53 MSPS 12 bit, AD converters
• Dual 165 MSPS 12 bit, DA converters
• System cost SEK6900, 100.000, 895
  (development software)

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Engine simulator
Experimental setup

• Desktop tests carried out during the development
• An in house device simulating Pcyl
  synchronously with CAD (3600/cycle) and TDC
  pulses (1/cycle)
• Pcyl emulated using 8bit and 720 samples/cycle
• DA conversion with R/2R ladder
• Pcyl originating from Scania D12 _at_ 1200 rpm

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System frequencies
Experimental setup
fmax45kHz
fCADP7.2-144kHz
fmax200kHz
fclk100-500MHz
fclk50-150MHz
fmax4kHz
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Design tools
Experimental setup

• The selection of appropriate development tools
  very important design issue
• Current implementation carried out using
  Matlab/Simulink
• Xilinx System generator DSP needed in order to
  use Simulink for design
• The standard blocks are not possible to use,
  necessary to possess a VHDL implementation (a
  number of those comes with SGDSP)

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New HR-net algorithmIssues with pressure
derivative
Algorithm
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Arithmetics
Algorithm

• Fixed point arithmetics were used for simplicity
• Input and output word length of 12bit
• Internal representation occasionally larger but
  still fixed point
• As many terms as possible mapped in RAM, (dV and
  V)
• Constants of course calculated and added off-line

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Engine synchronization
Algorithm

• Asynchronous operation relative to engine CAD
  enables very low latencies
• FPGA clocked at high time-based rate
• Counter based synchronization carried out with
  the CAD pulses
• The preferred method to obtain low latency

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Simulink design
Algorithm
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Successful implementation!
Results

• Main result, successful implementation
• Very high performance
• Current FPGA HR algorithm introduces a delay
  of 12 clock cycles gt 120 ns delay
• Engine _at_ 1200rpm moves 0.000864 CAD within 100ns,
  (0.01728 CAD _at_ 24000rpm)
• Negliable latency, virtual Q sensor!
• 50 MHz FPGA throughput (AD converter slowing
  down) ? 12 complete (1205 Sample) HR analysis
  / CAD _at_ 1200rpm

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Virtual sensor
Results
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80 Cycles average
Results
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Resolution
Results

• Based on Scania D12 metrics
• Plsb1465 Pa (0.24 of Pmax)
• Vlsb5.0510-7 m3 (0.24 of Vmax)
• dVlsb1.7410-9 m3/CADP (0.24 of dVmax)
• Qlsb3.85 J

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Non average
Results
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Hardware issues
Results

• The AD converters showed not to be plug n play
• Input stages had to be thoroughly modified,
  leaving issues with input bias and noise
• Output trigger signals of the fake engine jitters
  causing the synchronisation to the FPGA to
  sometimes falter
• CAD detection must be revised in order to
  increase the tolerance of faulty CAD and TDC
  pulses

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Implementation issues
Results

• Very difficult to implement the pressure
  derivative, many approaches were tested
• The transparency of the tool insufficient
• The support for internal synchronisation etc are
  rudimentary (insufficient)
• Many design steps had to be taken ad-hoc
• Very difficult to verify the correct
  number-resolution

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Conclutions
The posibility of using FPGA was shown

• It is possible implement an internal combustion
  analysis related algorithm in an ASIC/FPGA
  environment.
• Disregarding the synchronous thinking between the
  engine and FPGA board enables very low latencies
  without any major drawback.
• A modified algorithm makes it possible to
  calculate the cumulative heat release without the
  use of any (often noisy) pressure derivative.

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High gains in performance
Conclutions

• Extraordinary performance can be achieved using
  the described system
• A sample of Pcyl is processed and corresponding
  Qhr is calculated before any engine can move 0.02
  CAD
• A throughput of 50MHz enables the FPGA system to
  perform 12 1205 sample HR analysis within a
  single CAD _at_ 1200rpm
• Further performance improvement can easily be
  obtained through the use of more powerful hardware

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Two different publications

• Paper and Poster, Model based engine control
  using ASICs A Virtual heat release sensor
• Les Rencontres Scientifiques de lIFP New
  Trends in Engine Control, Simulation and
  Modeling
• 2-4 October 2006 IFP/Rueil-Malmaison, Paris
• Paper, F2006P039, FPGA Based Engine Feedback
  Control Algorithms
• 31st FISITA World Automotive Congress (organised
  by the Society of Automotive Engineers of Japan
  (JSAE) and FISITA).
• 22-27 October, Yokohama, Japan

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FPGA Continuation

• Change development environment
• Re-implement the HR based on the gained
  experience in the new environment
• Move on with more complex applications
• PID
• MPC
• Hybrid control

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Thank you for the attention