David Rich

1
Introducing HyperTransportTM 3.0
Mario Cavalli General Manager HyperTransport
Consortium

• David Rich
• President
• HyperTransport Consortium

Brian Holden Vice President Chair Technical
Working Group HyperTransport Consortium
2
HyperTransport ConsortiumOwns and Licenses
HyperTransport Technology
HyperTransport Consortium
Founded 2001 Mission The standardization of
a low latency, high-bandwidth interconnect
serving a broad range of next-generation
high-performance electronic industry applications
Founding Members
Joined by Tens of World Technology Leaders
From



to
3
HyperTransportTMProcessor-to-Processor,
Processor-to-I/O,Processor to High-Performance
Peripherals Interconnect
HyperTransport Profile
Industry answer to

• Best End-User Performance
• CPU Native
• Lowest Latency
• Highest Bandwidth
• Broad System Scalability
• 2-Bit to 32-Bit Links
• Asymmetric Links Support
• Easy Multiprocessor Scalability
• Minimum Silicon Deployment
• Less Control Logic
• Less Power Consumption

• HTXTM Connectivity
• Lowest Latency Direct Connect
• Between CPU(s and Peripherals via
• Standardized Direct HyperTransport Links
• 16-Bit or 8-Bit Wide
• 6.4GB/s Bandwidth
• Eliminates Performance Bottlenecks of
  Compute-Intensive
• Peripherals and Co-Processing Subsystems

4
Core Differentiators
HyperTransport Profile (cont.)
HyperTransportTM
()
5
Adopted by Technology Leadersin Widest Range of
Market Segments
HyperTransport Profile (cont.)
6
Market Statistics
HyperTransport Profile (cont.)
Summary Forecast of Worldwide HyperTransport
Systems 2003-2009 (Units in Thousands)
Source In-Stat 8/05
7
Interconnect Landscape
High Performance Interconnect Evolution
HyperTransport Delivers Widest Application
Latitude
8
Server Clustering
Major Industry Trends
Major Industry Trends Bank on HyperTransport
Performance/Cost-OptimizedData-Center Servers
Standard Interconnects Weave Off-the-Shelf
Servers into Powerful Scalable Clusters

• Core Compute and Storage Functionality
• No Legacy I/O Control Subsystem
• Clustered via High-Bandwidth
• Low Latency Multi-Gb/s Interconnect
• Cost Saving Times n Factor
• Reduced Power Consumption
• Increased Reliability

Server Clustering Makes HPC a Commodity!
Localized Legacy I/O Processing
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High-Performance Co-Processing Functions
Major Industry Trends Bank on HyperTransport
Compute-Intensive Applications Served by Standard
CPU Platforms Tightly Coupled With Application-Spe
cific Co-Processing Subsystems
DDR Memory
Commodity-Level Systems Minimize
TCO Co-Processing Approach Tailors Performance
to Application at Optimized System Cost
HTXConnector
Target Markets Low Latency Clustering Security
Monitoring Network Protocol Analysis Algorithm
Acceleration Storage Management Encryption/Decryp
tion Others
VacantOpteronSocket
Others
DDR Memory
10
Technology Milestones
HyperTransport Evolution
Chip-to-Chip
2001
2002
2003
2004
Chip-to-Chip and Beyond
2005
2006
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Why HyperTransportTM 3.0?
HyperTransport Evolution (cont.)

• Need for Lowest Latency and Highest Bandwidth
• Server Clusters
• Parallel Processing
• Co-Processing
• Design Flexibility
• Direct Cross-System Processor-to-Processor
  Interconnects
• Simplified Interconnect Protocol
• Intelligent System Configuration
• Escalating Power Consumption Concerns
• Lower Total Cost of Ownership
• Fewer Technologies Inside and Outside the Box
• Higher Reliability
• Support for Next Generation Processors
• Higher Throughput
• More Interconnect Links

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HyperTransport 3.0State-of-the-Art Specifications
State-of-the-Art Specifications
Same Features as HT 2.0 Plus

• 1.8 GHz, 2.0 GHz, 2.4 GHz and 2.6 GHz Clock
  Support
• 41.6 GB/s Aggregate Bandwidth
• 20.8 GB/s (166.4 Gb/s) per Link
• DC Operating Mode Enhancements
• AC Operating Mode (Optional)
• Supports Applications Requiring Greater Signal
  Interconnect Distance
• Cables
• Backplanes
• Larger Physical Systems
• Chassis-to-Chassis Interconnects
• DC/AC Auto-Configuration
• Link-Splitting/Un-Ganging Mode (Optional)
• Auto-configuration of Bi-Mode 2x8 or 1x16 Links
• Hot Plugging
• Backplanes Applications
• Power Management Enhancements (Optional)
• Support Dynamic Link Frequency and Width
• 100 Backward Compatibility
• Auto-Configuration at Boot-Up with Minimum Spec
  Common Denominator Selection

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Doubling Performance - Again ()
State-of-the-Art Specifications (cont.)
Twice HyperTransport 2.0s 16-bit Throughput With
No Increase in System Design Complexity and Real
Estate Penalty/Cost
HT 3.0 20.8 GB/s (Aggregate)
HT 2.0 11.2 GB/s (Aggregate)
1.4 GHz 1.8 GHz 2.0 GHz 2.2 GHz
2.4 GHz 2.6 GHz Clock
() HyperTransport 2.0 Doubled HyperTransport 1.x
Performance in February 2004
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DC Operational Mode Enhancements
State-of-the-Art Specifications (cont.)

• Transmitter
• Enhanced Training Pattern Tolerates Multi-Bit
  Skew
• Added Scrambling Enables Rx Phase Alignment
• Retained Clock Forwarding Scheme on Dedicated
  Lane(s)
• Maximized System Performance Predictability
  Scales with System Architecture
• Receiver
• Enabled Use of Rx Equalization
• Support for Multi-Bit Skew Through Clock-Based Rx
  Phase Alignment
• 100 Backwards Compatible
• Runs in HyperTransport 1.x and 2.0 Mode when New
  Features Not Enabled

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AC Operating Mode - Optional
State-of-the-Art Specifications (cont.)

• Supports Backplane, Board-to-Board,
  Chassis-to-Chassis Implementations
• AC-Coupling Capacitors
• 8B/10B for DC Balance
• Tx Equalization
• Lower Bandwidth, Higher Latency
  than DC Mode
• Enabled when Needed Best of Both Worlds

Transmit with Pre- and Post-Cursor De-Emphasis
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DC/AC Auto-Configuration
State-of-the-Art Specifications (cont.)

• Between Existing Low-Latency DC Mode and New
  Long-Reach AC Mode
• Circuitry Detects Presence
  of Coupling Capacitors
• Auto-Switches to AC Mode
• Allows System Vendors to Connect the Same
  HyperTransport Device in DC Mode for Short Runs
  and AC Mode for Long Runs

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Link-Splitting Mode - Optional(Un-Ganging)
State-of-the-Art Specifications (cont.)

• Auto-Configuration of Bi-Mode 2x8 or 1x16 Link
  Width
• More HyperTransport Ports Useful in Topologies
  Such As Symmetric Multi-Processing (SMP)
• Required by Vendors Interested in Dual-Mode
  Interfaces

2x 8-Bit Links
1x 16-Bit Link
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Link-Splitting AC ModePowerful Multi-processor
Expansion Capability
State-of-the-Art Specifications (cont.)
Chassis 1
Chassis n
To other CPU subsystems
To other CPU subsystems
CPU
CPU
CPU
CPU
Max 3.0 clock speed with cables up to 1m in length
To other CPU subsystems
To other CPU subsystems
CPU
CPU
CPU
CPU
HTX Connector
HTX Connector
I/O
I/O
8-Bit DC HyperTransport Links
16-Bit DC HyperTransport Links
16-Bit AC HyperTransport Links
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Hot Plugging
State-of-the-Art Specifications (cont.)

• Ability to Add /Remove Devices from
  HyperTransport Fabric Without Disrupting Other
  Operations
• Defined Link Termination Methods
• Transaction Termination Behaviors
• Sync Flood Isolation
• Link Training Times
• Parameter Configuration Mechanisms

Important in High-Availability Applications, Serve
r and Storage Markets
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Power Management Enhancements - Optional
State-of-the-Art Specifications (cont.)

• Dynamic Link Frequency and Width
• Allows Implementation to Dynamically Change
  Frequency and Width of a Link
• Rapid Pause-Change-Start Support
• Implements in Hardware

Answer to Increasing Importance of Power
Consumption
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Meeting Present and FutureApplication
Requirements
State-of-the-Art Specifications (cont.)
HyperTransportTM
Max Use Max Capable At Present 3.0
Specs Headroom

• Aggregate Bandwidth 8.0 GB/s 41.6
  GB/s 520
• Link Width 16-bit 32-bit
  100
• Clock Speed 1.0 GHz 2.6 GHz
  162
• Operational Mode DC
  DC or AC Distance

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HyperTransport 3.0 Already In Demand
Where from Here

• HPC System Manufacturers Consider HT 3.0 Highly
  Strategic for Next-Generation Product Roadmap
• Vastly Improved Processor-to-Processor
  Interconnect Flexibility and Performance
• In-Chassis and Chassis-to-Chassis
• Optimized Parallel Processing Operations
• SMP Architectural and Cost Optimization
• Server and High-Performance Workstation Companies
  Regard HyperTransport 3.0 as Painless Path to
  Performance Doubling of 16-Bit Link Designs
  without Added System Design and PCB Real Estate
  Complexity

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Questions and Answers
Introducing HyperTransport 3.0All product
trademarks included in this presentation are the
property of their respective owners
For more information about HyperTransport
technologyplease visit the Technology page on
our Consortiums web portal at www.hypertransport.
orgor call us at 925-968-0220