Low Energy Clustered Instruction Fetch and Split Loop Cache Architecture

1
Low Energy Clustered Instruction Fetch and Split
Loop Cache Architecture

• Murali Jayapala Francisco Barat
• Pieter Op de Beeck
• ESAT/ACCA, K.U.Leuven, Belgium

Francky Catthoor Rudy Lauwereins IMEC, Leuven,
Belgium
2
Problem

• Context
• Embedded Processor Architectures
• Multimedia Applications
• Low Power Embedded Systems
• Power Breakdown
• 43 of power in Memory
• StrongARM SA110 A 160MHz 32b 0.5W CMOS ARM
  processor
• 40 of power in internal memory
• C6x, Texas Instruments Inc.

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Problem
Significant Power consumption in Instruction
Memory Hierarchy
I-Cache
Instruction Decode
Active every instruction Cycle
DATAPATH
4
Outline

• The Approach
• Loop Cache
• Contributions
• Variance of power among different schemes
• not well analysed
• Splitting
• Results
• Conclusion

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The Approach

• Small sized loops in the application

• a of Execution cycles spent in the loops
• Employ Loop cache
• Approach 1
• Approach 2

6
Approach 1

• No Change in Pipeline
• Cache Control
• Hardware
• Automatic loop detection logic
• MCore, L. H. Lee et al
• Software
• Explicit placing of cache data
• N. Bellas et al

E C aPL0 (1-a) PL1 PD
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Approach 2

• Reduces pipeline stages
• Cache Control
• Hardware
• Automatic loop detection logic
• R. Bajwa et al
• TI Inc, T. Anderson et al
• Software
• -

E C aPL0 (1-a) PL1 (1-a) PD
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Energy analysis
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Extensions Split Loop Caches

• Clusters of instruction in loops with different
  code fields activated
• Address Calculations
• Index calculations
• Arithmetic and Logic Computations
• Computations on array elements
• ? (Psmall) ? Plarge

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Extensions 1

• No Change in Pipeline
• Cache Control
• Software
• Explicit placing of cache data through
  instructions

E C ?i (aiPL0i PDi) (1 - a) PL1
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Extensions 2

• Reduces pipeline stages
• Cache Control
• Software
• Explicit placing of cache data through
  instructions
• Local Controller
• Demand cache to feed cache
• Support for control constructs

LC
LC
E C ?i (aiPL0i (1 - a) PDi) (1 - a) PL1

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Splitting Vertical
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Results
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Conclusion

• Split loop cache architectures
• Further Power/Energy reduction
• Enables more compiler oriented optimizations
• Splitting
• Basic blocks
• Emphasis on vertical splitting of the code
• at granularity of
• Loops
• Instructions