Digitization of analogue signals from FE chips

1
LHCb will study the B-mesons produced in
collisions between two proton beams in the 'Large
Hadron Collider' (LHC) at Cern. The B-mesons will
travel about 7 mm before decaying (the decay
violates CP). Thus its very important to
reconstruct the decay vertex with high precision.
This is accomplished by the VErtex LOcator, which
consists of a row of silicon strip detectors,
each 200-300 ?m thick. The sensors are positioned
perpendicular to the beam at a radial distance of
8 mm. The silicon process of the detectors and
the Front End electronics is especially chosen
for the radiation hard environment. 5K analogue
links transport the signals out of the cavern.
RB1 (1999) 2 Channels _at_10 MHz
RB2 (2000) 4 Channels _at_40 MHz
ODE
The VELO is divided into 21 stations, each with 4
silicon sensors (2 in R and 2 in ?). Each sensor
has 2048 channels, which are read out by 16 FE
chips (gt 128 channels/chip). Each station will
then be connected to the Off Detector Electronics
via 4 analogue links/FE chip, which makes a total
of 64 analogue links for each Readout Board
(RB4). Since the ODE is located in the counting
room, use of standard components (as FPGAs and
DSPs) is allowed. ODE functionalities are the
following
RB3 (2002) 16 Channels _at_40 MHz
ECS
L1B Connector

• Digitization of analogue signals from FE chips
• Data is digitized by a 8-bit ADC _at_40 MHz.
• Done by FADC card.
• Synchronization, Error Checking and Event tagging
• Synchronization of different input channels.
• Error checking with FE emulator, TTC and
  neighboring channels.
• Event tagging using TTC information.
• Controlled by Fast Synchronization and Control
  (FSC) FPGA.
• Level 1 Trigger Preprocessing
• Pedestal subtraction and Faulty Channel Masking.
• Common Mode Noise Suppression and Hit detection.
• Re-Ordering and Cluster Encoding.
• Performed by Synchronization and L1 Pre Processor
  (SPP) FPGA.

FADC
L1 Link Card
SPP
FE Emu
TTC
DAQ Link
L1 Link
FSC
RB4 (2003) 64 Channels _at_40 MHz
L1B
L1B
Input
Input
L1B
L1B
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