CoE EE 00142 Computer Organization Set 10 InputOutput

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CoE - EE 00142Computer OrganizationSet 10 -
Input/Output

• Ron Hoelzeman

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Five Computer Components
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I/O Device Speeds
Fig 8.2
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Basic Computer Organization
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Computer Buses

• Bus - collection of signal wires that carry a
  binary number
• Word comes from Bus Bar
• big copper strips used to distribute electric
• Buses now used to distribute information
• between memory and cache, memory and disk, disk
  and I/O, etc.

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Computer Buses

• Physically - wires etched to back plane of mother
  board
• Logically - typical bus configuration
• address bus
• data bus
• control bus
• Parallel or serial

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6800 Bus Structure
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Typical Bus Structure
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Example Bus Signals

• Data bus - Bits (0 - n) of data
• Address bus - Bits (0 - n) of address
• Control bus examples
• Write address bus control line
• Write data bus control line
• Read address bus control line
• Read data bus control line

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Three State Buffer
When EN 1, output input When EN 0, output
Hi Impedance
Use the tri-state or three state buffer to
connect to any bus line
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Bus Arbitration

• Deciding who can read or write on the bus at a
  given time
• Control of source destination
• Deciding who is in control is called bus
  arbitration

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Daisy Chaining

• Unit requests use of bus - bus request
• Current user finishes, lowering -bus busy
• Arbitrator (logic unit) raises - bus grant
• Bus grant is passed down along the daisy chain
  until accepted by a unit which then raises - bus
  busy

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Daisy Chain Bus Structure
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Daisy Chain Bus Example
A - unit 3 has bus B - unit 4 requests C - unit 2
requests D - unit 3 releases E - unit 1 passes to
2 F - unit 2 takes bus unit 4 is still
waiting
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Fairness of Arbitration

• Unit closest to arbiter dominates
• highest priority
• Daisy chain called a priority chain
• Some units could be starved from the bus
• Priority - function of physical position
• Daisy chain slow

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Other Arbiters Philosophies

• Run separate request/grant lines
• flexible but lots of wires
• Arbiter can poll
• fair if round robin - start where it leaves off

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Independent Request - Grant Lines
Flexible - but lots of wires
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Polling Bus Structure
Fairer - if round robin polling
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General Classes of I/O

• Programmed input-output
• Interrupt driven
• Direct memory access

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Programmed Input Output

• Simplest form
• Specific commands to input or output data
• Wastes time
• Low transfer rate
• Uses accumulator for transfer

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Interrupt Driven I/O

• Provides for multiprogramming
• execute multiple programs concurrently
• Interrupt vector
• one memory address for each interrupt
• points to service subroutine
• Context switch
• saving register status and switching programs

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What are Interrupts

• An interrupt is a special event
• Causes CPU to stop normal execution
• Generated externally or internally
• Must provide for return to normal execution

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Types of Interrupts

• External
• Coordinates I/O activities
• Routine tasks time of day
• Internal
• Illegal Op Codes
• Traps and exceptions

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Interrupt Concepts

• Mask ability
• Allow some interrupts to be ignored
• Priority
• Allows some interrupts higher priority
• Service Routine
• The program initiated by the interrupt (example
  input keyboard character)
• Interrupt vector
• Starting addresses of service routines for each
  interrupt

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Normal Interrupt Process

• When an interrupt occurs
• Save the CPU status
• Identify the cause of the interrupt
• Resolve the starting address of the corresponding
  service routine
• Execute the service routine
• Restore the CPU status
• Restart the interrupted program

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Tannenbaum, Prentice Hall
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Example 68HC11 Interrupt System

• System supports
• 16 Hardware interrupts
• Real time clock, serial port, etc.
• 2 Software interrupts
• Divide by zero, overflow, illegal codes, etc.
• 3 Resets
• Power on, manual, etc.

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68HC11 Interrupt Vector Address and Priority
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68HC11 Interrupt Handling Procedure

• When an interrupt occurs
• CPU saves registers on stack
• I bit of CCR is set to a 1 to disable further
  interrupts
• Starting address of service routine is fetched
  from predefined table
• Program is executed at that address

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68HC11 Interrupt Stacking Order
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Example of Interrupt
Consider the following program segment
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Interrupt Overhead

• In the 68HC11
• Saving the CPU registers and fetching the
  interrupt vector address takes 12 clock cycles
• The RTI instruction restores the registers and
  takes an additional 12 clock cycles
• Interrupt total is 24 plus the service routine
  cycles

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Direct Memory Access

• Independent transfer of data from I/O to memory
• Instruction has start-stop locations
• Requires considerable extra logic
• Cycle steals

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Discrete Continuous Conversion

• Real world devices are analog or continuous
  signals
• To monitor or control requires conversion of
  signals
• Digital to analog - D/A
• Analog to digital A/D

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Digital-to-Analog Conversion
Let ai (0, const)
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Consider the effect of a0 on Vout
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Consider the resistance to the left of the node
with voltage V0
R??R R/2
etc.
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Then the resistance to the left of the node with
voltage V0 is simply R
Finally, using a voltage divider, V0
((R/2)/(RR/2)) a0 1/3 a0
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Now consider the portion of the voltage V0 which
exists across V1
V1 ((R/2) / (R/2 R/2)) V0 ½ V0
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Vout V3 (½)3 V0
then using superposition
Vout (½)2 V1
Vout (½)1 V2
putting it all together
Vout 1/3 (a3 ½ a2 (½)2 a1 (½)3 a0)
Let ai (0, 1) volts
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4 bit D/A converter
Let ai (0, const voltage)
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8-bit D/A Converter
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A/D Converter Subsystem
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Analog to Digital Conversion

• Typically uses D/A converter
• Example systems
• Using up counter
• Using up-down counter
• Using successive approximation

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A/D Using Up Counter
Simplest form Counts until analog signal B equals
A Always starts at 0
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A/D Using Up-Down Counter
Counts up or down until analog signal B equals
A Can start at previous reading
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A/D Using Successive Approximation
Tries MSB first, then moves on down to MSB-1
until signal B equals A
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End of Set
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