Programmable Logic Technologies

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ECE U322Digital Logic Design
Dec. 1, 2005

• Lecture 33
• PAL, PLA and Mapping Designs onto FPGAs
• Next weeks lectures will contain reviews

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PALs and PLAs

• PLA is the most flexible
• One PLA can implement a huge range of logic
  functions
• BUT many pins, large package, higher cost
• Each programmable connection needs extra space
• PALs are more restricted you trade number of OR
  terms vs. number of outputs
• Many device variations needed
• Each device is cheaper than a PLA

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PAL Logic Implementation
K-maps
Design Example BCD to Gray Code Converter
Truth Table
Minimized Functions
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Discrete Logic Implementation
Code Converter Discrete Gate Implementation
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PAL Logic Implementation
Minimized Functions
4 product terms per each OR gate
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Example Magnitude Comparator

• Inputs ABCD Outputs EQ, NE, LT, GT

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PLA Logic Implementation
Another Example Magnitude Comparator
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Complex Programmable Logic Devices

• Complex PLDs typically combine PAL combinational
  logic with FFs
• Organized into logic blocks
• Fixed OR array size
• Combinational or registered output
• Some pins are inputs only
• Usually enough logic for simple counters, state
  machines, decoders, etc.

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16V8 CPLD
OLMC (Output Logic MacroCell) has OR, FF, output
multiplexer and I/O control logic. Note that
OLMC output is fed back to input matrix for use
in other OLMCs.
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Field Programmalble Gate Arrays (FPGAs)

• FPGAs have much more logic than CPLDs
• 2K to 400K equivalent gates
• Requires different architecture
• FPGAs can be RAM-based or Flash-based
• RAM FPGAs must be programmed at power-on
• External memory needed for programming data
• May be dynamically reconfigured
• Flash FPGAs store program data in non-volatile
  memory
• Reprogramming is more difficult
• Holds configuration when power is off

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FPGA Structure

• Typical organization is 2-D array
• Configurable logic blocks (CLBs) contain
  functional logic
• Combinational functions plus FFs
• Complexity varies by device
• CLB interconnect is either local or long line
• CLBs have connections to local neighbors
• Horizontal and vertical channels use for long
  distance
• Channel intersections have switch matrix
• IOBs (I/O logic Blocks) connect to pins
• Usually have some additional C.L./FF in block

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FPGA Hardware Architecture

• IOBs Input/Output Logic Blocks
• Inputs and outputs to the circuit
• CLBs Configurable Logic Blocks
• Combinational logic Flip-Flops
• Interconnect
• PIP Programmable Interconnect Point
• PSM Programmable Switch Matrix
• Support for reprogramming

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FPGA Structure
IOB
IOB
IOB
IOB
Input/Output Block
CLB
CLB
CLB
CLB
Switch Matrix
SM
SM
SM
CLB
CLB
CLB
CLB
SM
SM
SM
CLB
CLB
CLB
CLB
Configurable Logic Block
SM
SM
SM
CLB
CLB
CLB
CLB
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A Simplified Logic Slice2 of these are in a CLB
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Combinational Logic on a Simplified Logic Slice
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Mapping a Function to a 4-input LUT
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Sequential Logic on a Simplified Logic Slice
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Combinational and Sequential Logic on a Slice
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Implement one bit of a register

• If L 1, Register should load new data
• Load data is D
• If L 0, register should shift in new data
• Shift data is S
• How to map to FPGA slice?

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Combinational and Sequential Logic on a Slice
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I/O BlockXilinx 4000 Family -- Simplified
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Programmable Interconnect Point (PIP)The basic
unit of programmable interconnect
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Xilinx Interconnect

• Programmable Interconnect
• Pass Transistors as switches

Usable by another net.
0
1
Stored bits determine switch state.
0
1
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Interconnect Switch Matrixes and Programmable
Interface Points
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Xilinx Architecture Summary

• CLBs sprinkled across chip in a regular array
• CLBs can implement any function of 4 input
  variables
• IOBs for interfacing to outside world
• Lots of different kinds of interconnect for
  efficient design

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Xilinx Design Process

• Step1 Design
• Two design entry methods HDL(Verilog or VHDL) or
  schematic drawings
• Step 2 Synthesize to create Netlist
• Translates V, VHD, SCH files into an industry
  standard format EDIF file
• Step 3 Implement design (netlist)
• Translate, Map, Place Route
• Step 4 Configure FPGA
• Download BIT file into FPGA

HDL code
Schematic
Synthesize
Netlist
Implement
BIT File
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Truth Table for Full Adder
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Implement a Full Adder with a ROM
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Map a Full Adder to a PLA
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Map a Full Adder to a PAL
All possible connections are shown
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Map a Full Adder to an FPGA
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Design a 101 string recognizer
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Implement on an FPGA