ECE 406

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ECE 406 Design of Complex Digital Systems
Lecture 6 Procedural Modeling
Spring 2007 W. Rhett Davis NC State
University with significant material from Paul
Franzon, Bill Allen, Xun Liu
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Summary of Last Lecture

• Does every numeric value have a corresponding
  logical value?
• How do you tell the difference between a bitwise
  operator and a reduction operator?
• How are vectors extended when operand lengths are
  mismatched?
• What operator would you use to implement sign-
  extension?

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Todays Lecture

• Sign-Extending Shifter Example
• LC-3 Instruction Format
• Intro to Procedural Modeling
• Control Constructs
• Inferred Latches

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Sign-Extending Right Shifter

• Design a Module that shifts a 4-bit input to the
  right 0 to 3 bits, depending on a shift input.
• Use only replication and conditional operators

in s out
1010 0 1010
1 1101
2 1110
3 1111
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Schematic for the Right-Shifter
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Sign-Extending Right Shifter

• module rightshift(output 30 out,input 30
  in, input 10 s)
• endmodule // rightshift

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Todays Lecture

• Sign-Extending Shifter Example
• LC-3 Instruction Format
• Intro to Procedural Modeling
• Control Constructs
• Inferred Latches

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LC-3 Instruction Format

• Opcode
• IR1512
• Addressing mode
• Immediate (sign extension)
• Register
• Memory PC relative MAR(PCoffset)
• Memory indirect MARMEM(PCoffset)
• Memory baseoffset MAR(SR2offset)
• In HW3, you are asked to design a sign-extension
  block for the LC-3 Microcontroller

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Sign-Extension in LC-3

• LC-3 has various ways of embedding immediate data
  and program counter (PC) offsets in an
  instruction word.
• Since LC-3 is a 16-bit architecture, well need
  to sign-extend this data to 16 bits so that it
  can be added to the PC, registers, etc.
• The part that needs to be sign-extended depends
  on the instruction
• Imm5 (Immediate Data ADD, AND)
• PCoffset6 (BaseOffset Addressing Mode LDR, STR)
• PCoffset9 (PC Relative Addr. Mode LD, LDI, LEA,
  ST, STI, BR)
• PCoffset11 (Subroutine JSR)
• Trapvect8 (Trap Routine TRAP)

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Operate Instructions
15 12 11 9 8 6 5 4
3 2 0

• ADD
• AND
• NOT

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Data Movement Instructions
15 12 11 9 8 6 5 4
3 2 0

• LD
• LDR
• LDI
• LEA
• ST
• STR
• STI

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Control Instructions
15 12 11 9 8 6 5 4
3 2 0

• BR
• JMP
• JSR
• JSRR
• RET
• RTI
• TRAP

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Todays Lecture

• Sign-Extending Shifter Example
• LC-3 Instruction Format
• Intro to Procedural Modeling
• Control Constructs
• Inferred Latches

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Parts of a Verilog Module

• Header module ltmodule_namegt (ltport_listgt)
• Parameter, Port, Variable declarations
• Functionality description
• Structural
• Instantiations of basic gates
• Instantiations of lower-level modules
• Behavioral
• Data-Flow (continuous assignments)
• Procedural (initial always blocks)
• Terminator endmodule

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Why Procedural Modeling?

• Needed for test-benches
• Can also use it to describe the hardware.Why
  would we want to?
• Needed to describe sequential logic
• What is sequential logic?

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Modeling Combinational Logic

• Generally, combinational logic is modeled with
  continuous assignments (Data-Flow modeling)
• But it can also be modeled procedurally
• More abstract than Data-Flow
• But probably only for hard core C programmers
• Allows the use of control constructs like
  if-then-else, case

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Initial Blocks

• Youre familiar with procedural blocksYou used
  one to implement a test bench
• Procedural blocks are special because the
  statements are assumed to be executed
  sequentially
• Unlike the Data-Flow (continuous assignment), for
  which the order doesnt matter

initial begin monitor(time, in0 b
in1 b sel b out b,
in0, in1, sel, out) in0 0 in1 1 sel
0 // vector 1 10 in0 0 in1 1 sel
1 // vector 2 10 finish end
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A Simple Procedural Example

• Assuming that A,B,C, and X are all 1-bit
  variables, what logic is implied by the
  procedural behavior below?
• If we had written this as a dataflow behavior,
  it would be illegal. Why?

XAB X(XC)
assign XAB assign X(XC)
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The always Block

• Use the following statement to define a
  procedural hardware blockalways _at_(ltevent
  listgt) ltassignmentgt or ltblockgtwhere
  ltblockgt is a sequence of assignments delimited by
  begin and end
• The ltevent listgt or sensitivity list gives the
  events that trigger the execution of the block

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Event-Lists

• Simply naming a variable in the event-list means
  that the block will be triggered whenever that
  variable changes
• Use the or keyword to list multiple variables
• In this example, what does the event-list need to
  be for the logic to behave as expected?

always _at_( ) begin
XAB X(XC) end
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Verilog 2001 Event-Lists

• Verilog 2001 allows the use of commas to separate
  events
• The special case of _at_() or _at_ can be used to
  indicate all signals referenced in any
  expression

always _at_( ) begin
XAB X(XC) end
always _at_( ) begin XAB
X(XC) end
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Incomplete Sensitivity Lists

• If we had written the block like this, what
  would happen?
• All combinational inputs MUST be in the
  event-list for the logic to be modeled properly!

always _at_( A ) begin XAB
X(XC) end
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A Complete Procedural Module
module and_xnor(X, A, B, C) input A, B,
C output X reg X always _at_( A or B or C
) begin XAB X(XC)
end endmodule // and_xnor

• Remember that assignments in procedural block
  must be to reg variables! (not wire variables)
• Otherwise, youll get an error.
• Synthesis tools will recognize that combinational
  logic is being modeled, and there will be no
  registers in the final hardware.

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A Complete 2001 Procedural Module
module and_xnor( output reg X, input
A, B, C) always _at_ begin XAB
X(XC) end endmodule // and_xnor

• Note that the output X is declared as a reg
  inside the port-list
• Note the use of _at_ (This is always advised when
  modeling combinational logic, in order to avoid
  the incomplete sensitivity list problem)

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Todays Lecture

• Sign-Extending Shifter Example
• LC-3 Instruction Format
• Intro to Procedural Modeling
• Control Constructs
• Inferred Latches

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Conditional Statements if-else

• if - else if - else has the following syntax.
• if (ltexpression 1gt) ltstatement 1gt
• else if (ltexpression 2gt) ltstatement 2gt
• else ltstatement 3gt
• If the logical value of ltexpr 1gt is true, ltstmt
  1gt is executed.
• If the logical value of ltexpr 1gt is false and
  the logical value of ltexpr 2gt is true then ltstmt
  2gt is executed.
• If the logical values of both ltexpr 1gt and ltexpr
  2gt are false, then ltstmt 3gt is executed.

Sutherland guide 10.3
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ALU Example if-else
Code fragment of a 16-bit arithmetic logic unit
(ALU) that performs one of 5 operations.
if (alu_ctrl 0) // alu_ctrl is 3 bits
ALU_OUT ALU_IN1 ALU_IN2 // add else if
(alu_ctrl 1) ALU_OUT ALU_IN1 -
ALU_IN2 // subtract else if (alu_ctrl 2)
ALU_OUT ALU_IN1 ALU_IN2 // and else if
(alu_ctrl 3) ALU_OUT ALU_IN1
ALU_IN2 // or else if (alu_ctrl 4)
ALU_OUT ALU_IN1 ALU_IN2 // exor else
ALU_OUT 16d0 // other 3 undefined
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Conditional Statements case
Sutherland guide 10.3
The syntax of the case statement is case
(ltexpressiongt) ltalternative 1gt ltstatement
1gt ltalternative 2gt ltstatement 1gt
ltalternative ngt ltstatement ngt
default ltdefault statementgt endcase
The value of ltexpressiongt is matched to
ltalternativesgt in sequence, For the first
ltalternativegt that matches, the corresponding
ltstatementgt is executed. If no alternatives
match, ltdefault statementgt is executed.
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ALU Example case
Using the previous example of an ALU, the
corresponding implementation using a case
statement is
case (alu_ctrl) 3d0 ALU_OUT ALU_IN1
ALU_IN2 3d1 ALU_OUT ALU_IN1 - ALU_IN2
3d2 ALU_OUT ALU_IN1 ALU_IN2 3d3
ALU_OUT ALU_IN1 ALU_IN2 3d4 ALU_OUT
ALU_IN1 ALU_IN2 default ALU_OUT 16d0

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case Comparison Details
The case statement literally compares 0, 1, x and
z values in the conditional expression bit-by-bit
with the alternatives.
Thus if the case expression is 4b10xz, the
comparison is looking for an alternative of
4b10xz. In other words an exact match is
required.
Also, if the sizes of the evaluated expression
and the alternative pattern are unequal, the
shortest field is extended with zeros so the
sizes are equal.
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Alternatives casex, casez
There are two variants of the case statement
defined by the keywords casex and casez.

• casex treats all x and z values in the case
  expression
• or alternatives as dont cares.

• casez treats all z values in the case expression
  or
• alternatives as dont cares.

The casex is useful when the state of certain bit
positions is immaterial in some of the
alternatives. By using casex in such situations,
it is possible to reduce the number of
alternatives needed.
Sutherland guide 10.3
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Procedural Examples

• reg 30 in1
• reg out
• reg 10 in2
• always_at_(in1 or in2)
• case (in2)
• 2b00 out in10
• 2b01 out in11
• 2b10 out in12
• 2b11 out in13
• endcase

• Muxes and Data Selectors
• reg 10 in1, in2, out
• reg in3
• always_at_(in1 or in2 or in3)
• if (in3) out in1
• else out in2

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Procedural Examples

• Decoder
• always_at_(address)
• case (address)
• 2b00 line 4b0001
• 2b01 line 4b0010
• 2b10 line 4b0100
• 2b11 line 4b1000
• endcase

• Priority Selector or Encoder always_at_(A or B
  or C) casex(A)
• 3b1xx out B
• 3b01x out C
• default out 2b0endcase

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Todays Lecture

• Sign-Extending Shifter Example
• LC-3 Instruction Format
• Intro to Procedural Modeling
• Control Constructs
• Inferred Latches

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Latches

• Complete the behavior below
• always_at_(clock or D)
• if (clock) Q D
• clock
• D
• Q
• We will not intentionally build latches in this
  class
• Instead, well stick to one type of timing
  element (edge triggered flip-flops)

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Inferred (Unintentional) Latches

• What is happening here?
• always_at_(A or B or C)
• begin
• D B C
• if (D) E C
• end

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Procedural Examples
always_at_(A or B) casex (A) 2b00 C B
2b01 C B endcase

• What about this?

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Procedural Examples

• Will this simulate correctly?
• always_at_(A)
• C A B

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Summary

• Does the order of procedural assignments matter?
  What about continuous assignments?
• What does the event-list of an always block mean?
• To model combinational logic procedurally, what
  variables must be in the event list?
• Should variables assigned in a procedural block
  be declared as wire, reg, or either?
• How do you prevent an unintentional latch?