Parallel and Serial Interconnects AMS I2'1'5 Fall 2005

1
Parallel and Serial Interconnects AMS I-2.1.5
Fall 2005

• Greg Phillips
• greg.phillips_at_rmc.ca
• Royal Military College of Canada
• Electrical and Computer Engineering

2
Hardware module

• topics
• fundamentals of digital systems
• computer system organization and CPUs
• gate logic (lab)
• parallel and serial interconnects
• internal system buses
• external device connections
• core memory
• secondary storage
• display and input devices

3
Typical System Architecture
ISA Devices
4
Internal CPU structure
memory data bus
memory address bus
M
AR
PC
DR
AC
ALU
IR
8-bit CPU interconnect bus
5
The problem

• imagine two components (chips, cards, etc), which
  must be connected together by 8 data lines and 8
  control lines

88 16 wires 16 pins per component
16
a
b

• now imagine that there are six such components,
  each of which must be connected to all others

16
c
b
16
16
16
16
240 wires 80 pins per component
16
a
d
16
16
16
16
e
e
16

• in general, the number of wires required to
  connect n components with w wires per connection
  is wn(n-1)/2 (e.g. 1665/2240) and the number
  of pins per component is w(n-1)

6
The general solution (bus)

• instead of this

16
c
b
16
16
16
240 wires 80 pins per component
16
16
a
d
16
16
16
16
e
e
16

• do this

96 wires 16 pins per component
b
c
d
e
f
a
16 bit data/control bus
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Whats a bus?

• a bus is nothing more than a bunch of wires

b
c
b
c
16
a
a
8
The general solution (bus)

• instead of this

16
c
b
16
16
16
240 wires 80 pins per component
16
16
a
d
16
16
16
16
e
e
16

• do this

96 wires 16 pins per component
b
c
d
e
f
a
16 bit data/control bus

• new problems
• 1. how to ensure that when a puts data on the bus
  that is intended for b, b reads the data and the
  other components ignore it
• 2. how to control who puts data onto the bus, and
  when

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Addressing

• problem 1
• when a puts data on the bus that is intended for
  b, b must read the data and the other components
  must ignore it
• solution
• add an address bus that we use to select which
  component data on the bus is intended for
• assert the components address on the address
  bus, decode the bus lines into an enable input
• for n components, require log2n address lines

96 18 wires 16 3 pins per component
for decode logic
3 bit address bus
b
c
d
e
f
a
16 bit data/control bus
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Decode logic

• each component connected to the bus must enable
  or disable itself according to the address
• usually includes internal enable/disable signal
  connected to address decoder

a0
a1
a2
3-to-8 decoder
s0
s1
s2
s3
s4
s5
s6
s7
s8
enable
component 2
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Single bus master

• problem 2
• how to control who has access to the bus, and
  when
• solution 2a
• single bus master declare one of the components
  (usually the CPU, say a) to be the bus master
  all communication coordinated by it
• bus master is only component allowed to assert
  values on address lines other components act as
  bus slaves
• so for information to move from b to c, the bus
  master (a) assert bs address on the address bus
  and read a value from the data bus, then put cs
  address on the address bus and write that value
  back to the data bus itself

3 bit address bus
96 18 wires 16 3 pins per component
b
c
d
e
f
a
16 bit data/control bus
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Multiple bus master

• single bus master is slow when data moves between
  non-master components (two bus cycles per
  transfer)
• typical case is where one of the components is
  memory, many of the other components need to
  read/write memory
• solution 2b
• multiple bus master each component can act the
  bus master
• for information to move from b to c one of the
  two (say b) becomes the bus master, asserts cs
  address on the address bus, and reads from the
  data bus
• new problem
• controlling who gets to be bus master
• typically handled by special bus arbitration
  logic (either at a particular point on the bus,
  or cooperative between all connected components)
  which allows components to request control of the
  bus and grants requests according to some policy
• normally takes at least one bus cycle to perform
  arbitration, however still significantly faster
  if the component becoming bus master needs to
  move a lot of data

13
Timing

• timing constraints arise from the fact that logic
  gates require some fixed period of time to
  undergo each change
• some amount of time is required for a voltage to
  travel the length of a given bus.
• a timing diagram is a pictorial representation of
  the sequence of events which must occur during
  the transfer of data between units
• much of bus design involves specifying the
  required timing relationships between events

address
by master
data enable
data
14
PCI bus

• Peripheral Component Interconnect (1992 onwards)
• up to 8 devices per bus
• typically only 3 or 4 cards allowed due to
  electrical issues
• supports multiple masters
• 32 or 64-bit data and address buses
• 94 pins (98 for bus master)
• multiplexed same pins are used for address as
  for data
• 33, 66 or 133 MHz clock
• maximum throughput 900 MB/s
• variants SmallPCI, IndustrialPCI, CompactPCI

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Typical System Architecture
ISA Devices
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Intel 840-based system (c. 2001)

• Surprise! The heart of a modern computer system
  isnt the CPU or the memory its the internal
  input-output chipset
• common to virtually all computer systems
• typical Intel configuration
• host bridge or memory controller hub (MCH)
• co-ordinates communications between CPU, memory,
  and graphics
• bus bridge or I/O controller hub (ICH)
• co-ordinates communications between CPU, memory,
  disks, and internal and external devices
• for custom applications, typically implemented as
  a CPLD or FPGA

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Internal and external

• purpose of internal buses is to interconnect
  components that are part of the computer
• purpose of system input/output technologies is to
  allow the computer to connect to outside devices
• the distinction is actually not clear
• some bus-type technologies can be extended
  outside the box
• some I/O technologies are used inside the box
• some I/O technologies include bus-like features
• multiple devices on one set of wires, addressing,
  etc
• and may even include bus in their names
• e.g. Universal Serial Bus (USB)

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Serial versus Parallel I/O

• Serial
• one bit at a time
• one signal wire, or possibly one for each
  direction
• slower at a given clock speed
• thinner cables
• smaller connectors
• cables can be long

• Parallel
• many bits at a time
• multiple signal wires
• faster at a given clock speed
• thicker cables
• larger connectors
• cables must be short
• multiple wires can electrically interfere with
  one another

Parallel bus interference problem gets worse as
bus clock frequencies increase.
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Serial buses rule!

• for external applications, serial buses have
  become the standard
• USB, Firewire
• for internal applications, parallel buses still
  the mainstream
• starting to change as clock frequency
  requirements and cable lengths increase
• new standard for disk access is serial ATA, in
  internal serial bus

20
Parallel to Serial Conversion

• data inside the computer in parallel (multiple
  wire) form
• must be converted to serial form for transmission
  and vice versa
• typically done by UART (Universal Asynchronous
  Receiver/Transmitter)
• includes buffers, shift register
• may also include start bit, stop bit, parity bit
• start and stop bits signal beginning and end of
  byte
• if even number of 1s in byte, parity 0, otherwise
  parity 1

1
0
0
1
1
1
0
1
shift register
transmit data line
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Key USB characteristics (USB 2.0)

• 480 Mb/s total bus bandwidth
• each device may request up to 12 Mb/s dedicated
  bandwidth
• up to 127 devices (plus the host) may be on the
  bus
• a host may provide multiple buses (may computers
  provide 2 or 4)
• devices are connected either directly to the host
  or through external hubs
• not chained, however, some devices may have
  built-in hubs, e.g., USB keyboards that provide a
  USB connector for a mouse, so it may look like
  devices are chained

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USB cabling

• four-wire cable
• power, power ground, two signal wires
• low-power devices (e.g., mice) can use bus power
  higher power devices (e.g., printers) must be
  self powered
• each cable not longer than 5m
• cables can be connected to hubs, which provide
  power and allow extra devices
• not more than 6 cables (30m) from a device to the
  host

A connector (host end)
B connector (device end)
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USB bus function

• on system start up or when a new device is added,
  the host automatically
• assigns each device a bus number
• interrogates each device to allow automatic
  selection of communication mode, driver software
• communication modes
• control mode
• used mainly for initialization by the host
• interrupt mode
• used by devices that have small, intermittent
  amounts of data (e.g., keyboards, mice)
• bulk mode
• used by devices that require large data transfers
  with 100 reliability (e.g., digital cameras,
  disk drives, PDAs)
• isochronous mode
• used by devices that require real-time
  performance but can tolerate data loss (e.g.,
  audio and video devices)

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USB data transmission

• all communication initiated by the host via a
  polling mechanism
• in essence, asks each device in turn whether it
  has data to send
• exception a device can issue a remote wakeup
  request to the host
• interrupt mode and isochronous mode devices are
  assigned dedicated time slots on the bus as part
  of initialization
• may consume up to 90 of available bus bandwidth
• if further device attempts to connect, host will
  refuse
• for isochronous devices, data transferred on a
  regular basis, e.g., every 40 ms
• for interrupt mode devices, polled on a regular
  basis to see if they have any data to transmit
• bulk mode devices get whatever bandwidth is left
  over
• if few other devices on bus, transfers will be
  fast otherwise data may trickle out over a
  long period of time

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Next class

• Core Memory