Lecture 22: Virtual Memory II

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Lecture 22 Virtual Memory II

• Why not use flat physical address space
• Protection between program
• Extend program space beyond DRAM capacity
• Today
• Segmentation
• Virtual memory paging
• Where do we put the page tables?
• How can we speed up access?

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Physical Memory Addressing
LW R1,0(R2)
DRAM 64MB
CPU
Cache

• 4 bytes per word
• 4 words per block

22 bits
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Segmentation

• Break up memory space into segments
• Segments placement and size can vary over time
• Solves relocation and Protection
• Memory accesses use base and length registers
• But - what about accessing more memory?

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Providing Protection Between Programs(Length
Registers)
Sys Code
Sys Table
Base 0

• Add a Length Register LR to the hardware
• A program is only allowed to access memory from
  BR to BRLength-1
• A program cannot set BR or LR
• they are privileged registers
• But how do we switch programs?

Code
Data

Length 0
Stack
Base 1
Code
Data

Length 1
Stack
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Main Memory as a Cache for Disk (Paging)
data page
(1-4KB)
Demand Paging

• 32 bit addresses 4GB, Main Memory 64MB
• Dynamically adjust what data stays in main memory
• Page similar to cache block
• Note file system gtgt 4GB, managed by O/S

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Virtual Addresses Span MemoryDisk

• Mappings changed dynamically by O/S
• In response to users data accesses
• OS triggered by hardware

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A Load to Virtual Memory
LW R1,0(R2)
DRAM 64MB
CPU
Cache
Translate
22 bits

• Translate from virtual space to physical space
• VA ? PA
• May need to go to disk

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Virtual Address Translation
11
31
0
12
Translation Table
0
12
25
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Physical Page Number (PPN)
Page Offset

• Main Memory 64MB
• Page Size 4KB
• VPN 20 bits
• PPN 14 bits

• Translation table
• aka Page Table

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Page Table Construction
Page Table Register

• Page table size
• (14 1) 220 4MB
• Where to put the page table?

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What if Data is Not in DRAM?

• 1) Examine page table
• 2) Discover that no mapping exists
• 3) Select page to evict, store back to disk
• 4) Bring in new page from disk
• 5) Update page table

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Page Fault
User Program Runs
User program resumes
Page fault
OS Installs page
OS requests page
Disk read
Disk interrupt
2nd User Program Runs
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VM Requires

• Restartable (or resumable) instructions
• must be able to resume program after recovering
  from a page fault
• Ability to mark a page not present
• and raise a page fault when referencing such a
  page
• (Optional) Maintain status bits per page
• R - referenced - for use by replacement algorithm
• M - modified - to determine when page is dirty

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Page Frame Management

• OS maintains
• page table for each user process
• page frame table
• free page list
• pages evicted when number of free pages falls
  below a low water mark.
• pages evicted using a replacement policy
• random, FIFO, LRU, clock
• if M-bit is clear, need not copy the page back to
  disk

Free
Link
Proc 1
Page Frame Table
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Page Management and Thrashing
W
Z
Z
Z

• Need to keep a process working set in memory or
  thrashing will occur
• Find working set size by increasing page frame
  allocation until PF/s falls below limit
• Swap out whole process if insufficient page
  frames for working set

X
X
W
W
Y
Y
Y
X
Reference four pages in sequence, mapped to three
page frames
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Page Table Organization

• Flat page table has size proportional to size of
  virtual address space
• can be very large for a machine with 64-bit
  addresses and several processes
• Three solutions
• page the page table (fixed mapping)
• what really needs to be locked down?
• multi-level page table (lower levels paged -
  Tree)
• inverted page table (hash table)

PTP
2n-o
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Multi-Level Page Table
Dir1
Dir2
Page
offset
PTP
Directory Directory
Page Directory
e.g., 42-bit VA with 12-bit offset10-bits for
each of three fields1024 4-byte entries in each
table (one page)
Page Table
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Inverted Page Tables
Virtual Address
Page
Offset

• Store only PTEs for pages in physical memory
• Miss in page table implies page is on disk
• Need KP entries for P page frames (usually K gt 2)

Hash
Page
Frame
S

OK
Frame
Offset
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How Long does it Take to Access VM?
Best Case
Worst Case
Fetch Page Table Entry
Translate VA?PA
Fetch data using PA
Translate Page Table Address
Issue Load

• Problems
• Multiple memory and potentially disk accesses
• Where does the cache fit in?
• Lets accelerate this process!

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Translation Lookaside Buffers
PID
Page
Offset

• Store most frequently used translations in small,
  fast memory
• On miss - two approaches
• hardware state machine walks the page table
• fast but inflexible
• exception raised and software walks the page
  table
• Valid, Writeable, Referenced, Modified
• Access protection
• Replacement strategies

TLB
VWRM
Page
Frame
Page VPN Frame PPN
Frame
Offset
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VM and Multitasking

• Virtual Memory Provides Protection
• Every user process has own virtual address space
  (own page tables)
• O/S can see through protection
• However - must prevent alias problems
• Two solutions
• Flush TLB on process switch/system call
• TLB includes process ID
• Caching issues - next time!

Program A
Program B

VA
?
PA
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Virtual Memory Implementation Tradeoffs

• Page Size
• TLB Miss rate
• Fragmentation
• Disk transfer time
• TLB
• Size
• Associativity
• Page table organization
• Inverted, multilevel, paged

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Segmentation vs. Paging
Paging
Segmentation

• Relocation
• Place data on any physical page
• Protection
• Separate address spaces
• Problems with sharing data among processes
• Resource Management
• Page sizes

• Relocation
• Base address register
• Protection
• Length register
• Resource Management
• Nothing

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Segmentation and PagingConceptual View
Segmentation Translation (Protection, Sharing)
Paging Translation (Resource Management)
LNS1
LNS2
Physical memory
Process Virtual Address Spaces (LNSs)
Absolute Address Space UIDs
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Next Time

• Virtual Memory III
• VM and caching
• Case studies of real VM systems