Logic Redesign for Low Power ELEC 6970 Project Presentation

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Logic Redesign for Low PowerELEC 6970 Project
Presentation

• By Nitin Yogi

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Outline

• Low Power Logic Synthesis
• Low Power Optimization Techniques
• Redundancy Insertion
• Logic Transformation
• Multiplier Cell Optimization
• Experimental Results
• Summary and Conclusion
• What I learnt !

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Low Power Logic Synthesis

• Sources of Power
• Dynamic power
• Signal transitions
• Logic activity
• Glitches
• Short-circuit
• Static
• Leakage
• Power a Area
• Method Area optimized logic synthesis
• Power a Transistor Leakage and Short-circuit
  current
• Method Optimized transistor level design for
  gates
• Power a Signal Activity of Circuit
• Method Low Power Logic Synthesis

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Low Power Optimization techniques

• Technology Independent Optimization
• Algebraic Logic Restructuring
• Kernel and Cube Extraction
• Iterative extraction and re-substitution of
  sub-expressions
• Post Mapping Structural Optimization
• Redundancy Insertion
• Logic Transformations

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Post-mapping Structural Optimization Redundancy
Insertion

• Redundancy is inserted into the circuit to
  minimize a cost function.
• 3 elements required in the process
• Suitable circuit location for redundancy
  insertion
• Candidate type of redundancy
• Cost function
• 3 steps involved
• Identifying candidates for redundancy insertion
  at a suitable circuit location for minimum cost
  function.
• Applying logic transformation to insert
  redundancy
• Reducing the circuit by removing other generated
  redundancies by logic transformation.

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Post-mapping Structural Optimization

• Finding Circuit Locations for Redundancy
  Insertion
• Identify Source and Target locations using dont
  care implications

Possible target location
x
x
A
x
x
x
B
0
Y
0
C
Source location
D
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Post-mapping Structural Optimization

• Candidate Redundancy insertions
• Redundancy insertions to input of gates
• Used to reduce signal activity at the output of a
  gate using another signal.

x
x
0
1
0 implication dont care
1 implication dont care
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Post-mapping Structural Optimization

• Gate Insertion

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Post-mapping Structural Optimization

• Circuit Reduction to eliminate unwanted
  redundancies
• Redundancy identification methods
• ATPG based
• Use of exhaustive ATPG to find redundant faults
• Redundant faults signify redundant logic
• Fault independent
• Controllability and Observability analysis

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Post-mapping Structural Optimization Logic
Transformations

• Permissible function
• If all the network primary output functions do
  not change after the function realized at a
  signal line Li is replaced by a function f , then
  the function f is called a permissible function
  for the signal line Li .
• Gate Substitution
• Replace a target signal line with the candidate
  signal line having the same function.
• Inverter Insertion
• Replace a target signal line with the inverted
  candidate signal line having the same function.

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Post-mapping Structural Optimization Logic
Transformations

• Eliminate inverters on signals with high activity
• Discourage the implementation of EX-OR gates
• EX-OR gate example
• Y AB AB
• (AB) (AB)
• (A B) AB

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Multiplier Cell
Full Adder
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Multiplier Cell
EX-OR
EX-OR
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Multiplier Cell Modified
EX-OR
EX-OR
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Multiplier Cell Modified - 2
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Multiplier Cell Leonardo (delay optimized)
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Multiplier Cell Leonardo (area optimized)
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Experimental ResultsMultiplier Cell

• Design and simulation details
• Design Entry tool Design Architect
• Simulation tool Eldo (timing and power
  analysis)
• Technology library tsmc 0.18um (VDD 1.8V)
• Input Vectors
• Inputs frequencies in multiples of 2
• Output transitions generated
• Sum Out (Sout) 25
• Carry Out (Cout) 12

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Multiplier Cell Results
Unopt. Opt. Leo_Area Leo_Delay
Static Power Static Power 367.04 pW 201.93 pW 168.94 pW 194.28 pW
Dyn. Power Dyn. Power 27.08 uW 17.39 uW 20.83 uW 21.28 uW
Tdelay (A/BgtSout) Avg. 276.13 ps 287.77 ps 225.85 ps 189.16 ps
Tdelay (A/BgtSout) Peak 328.45 ps 345.74 ps 257.23 ps 255.17 ps
Tdelay (A/BgtCout) Avg. 226.08 ps 173.77 ps 80.59 ps 90.16 ps
Tdelay (A/BgtCout) Peak 237.07 ps 177.02 ps 108.62 ps 96.60 ps
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Summary and Conclusion

• Post Mapped Structural Optimization techniques
  for Low Power prove to be effective.
• Percentage reduction in power consumption of
  optimized Multiplier Cell as compared to
• Unoptimized cell 35.7
• Leonardo generated 15
• Percentage increase in critical path delay of
  optimized Multiplier Cell as compared to
• Unoptimized cell 35.7
• Leonardo generated 50
• Effective cost functions to include delay
  constraints will enhance the quality of the
  circuits.
• Effective algorithms for structural optimization.
• 32 x 32 bit Multiplier power optimization.

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What I learnt !

• Low Power Logic Synthesis
• Logic synthesis
• Logic optimization
• Redundancy insertion, identification and
  elimination
• Use of EDA tools for timing and power analysis
• Start your projects early! (wish I would have)
• Large patience required with EDA tools!

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References

• S. Devadas, S. Malik, A Survey of Optimization
  Techniques Targeting Low Power VLSI Circuits,
  Annual ACM IEEE Design Automation Conference,
  Proceedings of the 32nd ACM/IEEE conference on
  Design automation, San Francisco, California,
  United States, pp. 242 247, 1995
• Pradhan D.K., Chatterjee M., Swarna M.V., Kunz W,
  Gate-level synthesis for low-power using new
  transformations, Low Power Electronics and
  Design, 1996, International Symposium on, pp
  297-300, Aug 1996
• Wang Q., Vrudhula S.B.K., Multi-level logic
  optimization for low power using local logic
  transformations, Computer-Aided Design, 1996.
  ICCAD-96., 1996 IEEE/ACM International Conference
  on10-14 Nov. 1996 Page(s)270 277
• Shih-Chieh Chang, Marek-Sadowska M, Perturb And
  Simplify Multi-level Boolean Network Optimizer,
  Computer-Aided Design, 1994., IEEE/ACM
  International Conference on November 6-10, 1994
  Page(s)2 - 5
• R. V. Menon, S. Chennupati, N. K. Samala, D.
  Radhakrishnan and B. Izadi, Power Optimized
  Combinational Logic Design, Proceedings of the
  International Conference on Embedded Systems and
  Applications, pp. 223 - 227, June 2003.
• W. Kunz, Multi-level Logic Optimization By
  Implication Analysis, Computer-Aided Design,
  1994., IEEE/ACM International Conference on
  November 6-10, 1994 Page(s)6 - 13

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References

• Roy K., Prasad S.C., Circuit activity based
  logic synthesis for low power reliable
  operations, Very Large Scale Integration (VLSI)
  Systems, IEEE Transactions onVolume 1,  Issue
  4,  Dec. 1993, pp 503 513
• Ki-Wook Kim, Ting Ting Hwang, Liu C.L., Sung-Mo
  Kang, Logic transformation for low power
  synthesis, Design, Automation and Test in Europe
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  pp158 162, March 1999
• Brzozowski I., Kos A., Minimisation of power
  consumption in digital integrated circuits by
  reduction of switching activity, EUROMICRO
  Conference, 1999. Proceedings. 25th Volume 1, 
  8-10 Sept. 1999 Page(s)376 - 380 vol.1 M. A.
  Iyer and M. Abramovici, Low-Cost Redundancy
  Identification for Combinational Circuits, in
  Proc. 7th International Conf. on VLSI design, pp.
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• V.D. Agrawal M.L. Bushnell, Qing Lin,
  Redundancy identification using transitive
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• Abramovici M., Iyer M.A., One-Pass Redundancy
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  1992 Page(s)807

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Thank You!

• Questions ???