Hierarchical Approach to Exact Symbolic Analysis of Large Analog Circuits

1
Hierarchical Approach to Exact Symbolic Analysis
of Large Analog Circuits
Sheldon Tan, Weikun Guo and Zhenyu Qi Department
of Electrical Engineering University of
California at Riverside
2
Outline

• Introduction and Motivation
• Review of Hierarchical Circuit Analysis
• Hierarchical Circuit Analysis
• Symbolic Cancellations in Hierarchical Circuit
  Analysis and Modeling
• Hierarchical Symbolic Circuit Analysis
• Cancellation-Free Expressions
• Symbolic De-cancellation strategy
• Experimental Results
• Summary

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Introduction

• Design Automation for Mixed-Signal SoCLags
  Behind DA for Digital Circuits
• Analog/MS/RF circuits are mainly crafted byhands
  due to lack of DA tools.
• IP-based analog designs promises reducing the
  design productivity gap for analog/MS circuits.
• IP-based MS-SoC design diagrams require accurate
  behavioral modeling across many design abstract
  levels
• Analog Hardware Description Language
  (AHDL)provide powerful modeling tools.
• But automatic generation of behavioral modelsis
  a difficult task

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Motivation for Symbolic Analysis

• Symbolic Analysis for Behavioral Modeling
• Symbolic analysis is an ideal tool for analog
  circuit behavioral modeling

However, number of symbolic terms grow
exponentially with complexity of circuits
For a ladder circuit with n node, matrix
element is 3n -2, whereas product terms is
F(n1), the memory required is O(nF(n1)).
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Review of Hierarchical Symbolic Analysis
Approaches

• Hierarchical symbolic circuit analysis can
  copewith large circuit sizes.
• Review of existing algorithms
• Topological decomposition (StarzkyTCAS86)
• Circuit decomposition on signal graphs via
  one-stepGaussian elimination using sequence of
  expressions
• Network formulation (HassounTCAS95)
• Circuit decomposition on circuit matrix via
  one-stepGaussian elimination using sequence of
  expressions
• Determinant Decision Diagrams (TanTCAD00)
• Circuit decomposition on circuit matrix via
  blockGaussian elimination using sequence of DDD
  graphs
• Main limitations
• Both sequence of expressions and sequence of
  DDDgraphs are difficult to manipulate
  symbolically other than numerical evaluations.

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DDD-based Hierarchical Symbolic Analysis
TanTCAD00
Block Gaussian Elimination
Sequence of DDDs graphs All the determinant
and first-order cofactors are represented by
DDD graphs
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Symbolic Cancellation in Hierarchical Analysis

• Cancellations are all caused by subcircuit
  reduction during hierarchical analysis
• Two types of cancellations (TanICCAD03)
• Term cancellation (abc bac 0)
• Common-factor cancellation (abc/ade bc/de)

Reduction
Reduction
STA
MNA
NA
Cancellation-free
Not cancellation-free
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Cancellation-Free Symbolic Expressions

• Cancellation-free expressions versus exact
  symbolic expressions
• DDD graphs are very amenable for symbolic term
  de-cancellation (TanDATE99)

Theorem 1 Cancellation-free expressions from
hierarchical symbolic analysis are equivalent to
exact symbolic expression obtained from flattened
circuit determinants
Hierarchical exact symbolic analysis Remove all
the symbolic cancellations
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Symbolic De-Cancellation An example

• Basic Idea Construct cancellation-free DDDs
  given a cancellation-bearing DDD

Reduce v1 and v2
terms 6
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The DDD Graph for the 3x3 Matrix
at1
Two Product terms (at1)(bt2)d (at1)ef
bt2
e
d
f
1
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Cancellation-Free Partial DDDs (PDDDs) and
Complementary DDD (CompDDDs) Graphs
Partial DDDs
2
2
1
1
a
det(A)
a
t2
b
t1
b
Original DDDs become 4 partial DDDs and 4
complementary DDDs Total terms 6
e
e
d
d
d
d
t1 t2
f
f
1
1
1
1
(a)
(b)
(c)
(d)
det(A)
t1
t1 t2
t2
a
x13
x24
x13
x24
d
x31
x42
x31
x42
a22
a11
1
?11
1
?22
?11,22
Higher-order cofactor after de-cancellation
Complementary DDDs
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Hierarchical Subcircuit Expansion Process
BFS process (top-down)
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Characteristics of PDDDs and CompDDDs

• Number of PDDDs and CompDDD can grow
  exponentially.

Theorem 2 if the size of AII is m and size of
ABB is l, then the maximum number of PDDD graphs
is bounded by where
and
But number of PDDDs can be limited by either
number of boundary nodes or size of internal
nodes of a subcircuit
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Constructions of PDDDs and CompDDDs

• Build PDDDs and CompDDDs for each DDD node in a
  bottom up fashion (DFS order).
• Make sure all the row and column indices of
  first-order cofactors in CompDDD are unique
• At each DDD node P
• Multiply P with PDDD List and CompDDD List from
  P.child1.
• Add the result from (1) with PDDD List and
  CompDDD List from P.Child0.

Time complexity for O(DDDk), DDD is the
final DDD size and k is number of subcircuits.
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Experimental Results
UA725 node 32 terms 1.21e8 Has been analyzed
exactly Symbolically for the first
time Analysis time 5s
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Experimental Results
Mesh-structured analog filter circuits with 100
nodes have been analyzed
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Summary

• Proposed efficient hierarchical exact symbolic
  analysis techniques
• Based on Determinant Decision Diagrams
• We proposed an efficient de-cancellation
  algorithm, which leads to hierarchicalDDD
  construction
• General analog circuit with about 100 nodes can
  be analyzed exactly for the first time.
• Significantly improve the exact symbolic analysis
  capacity and open a new application for exact
  symbolic analysis and analog circuit behavioral
  modeling