Application of FinFET Technology to AnalogRF Circuits Matthew Muh, Professor Ali M' Niknejad

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Application of FinFET Technology to Analog/RF
CircuitsMatthew Muh, Professor Ali M. Niknejad
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Research plans

• Evaluating the suitability of FinFET technology
  for analog/RF circuits involves the following
• Developing a working model for SPICE simulation
  based on 3-D device simulation
• Finding optimal device layouts for high-frequency
  performance
• Designing, fabricating test circuits (LNA,
  oscillator) and verifying power gain, noise,
  linearity
• Refining device models based on circuit-level
  measurements
• Comparing utility of FinFET for different
  applications

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RF CMOS performance trends

• Effect of technology scaling on RF performance
• fT improves with scaling (1/L for short-channel
  devices)
• fMAX improves with scaling, but limited by
  strong dependence on gate resistance and
  parasitics
• FMIN decreases with scaling for a given
  frequency
• IIP3 Id/W must increase to maintain good
  linearity
• Can a sub-100nm advanced transistor structure
  (FinFET) take advantage of these scaling trends
  and confer additional benefits to analog/RF
  circuits, e.g. better noise performance, improved
  gmro?

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High-frequency modeling

• Impact of gate resistance on RF performance
• if ignored, potential error in impedance matching
  (e.g., to a 50-O source)
• increased minimum noise figure
• reduced power gain, degraded overall
  transconductance
• fMAX
• Gate resistance modeling
• Rgate consists of two components
• distributed gate electrode resistance
• channel-induced gate resistance
• Minimize gate resistance by using
• gate contacts on both ends
• proper layout (short multi-gate finger
  structures)
• silicided poly-gate/metal gate technologies

Source Jin, IEDM98
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FinFET structure and layout

• The double-gate FinFETa promising candidate to
  continue CMOS scaling deep into the nanometer
  regime
• Gate straddles thin silicon fin, forming two
  conducting channels on sidewall

3D view of FinFET

• Layout similar to conventional SOI MOSFET

Source (all images) T-J King, et al, FinFET
Technology Optimization presentation slides,
Oct. 2003
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FinFET modeling

• Need a suitable SPICE model for initial design
  based on transistor I-V, C-V, and AC
  (S-parameter) characteristics
• Initial simulations based on BSIMSOI3.1 using
  preliminary SPAWAR (DC) model. BSIM DG currently
  under development.
• Need to verify high-frequency behavior of SPICE
  model
• BSIMSOI3.1 includes RF functionality and has been
  incorporated into spice3
• How to obtain RF model parameters?

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Future work

• Run 3-D device simulations using ISE DESSIS to
  extract high-frequency Y-parameters
• Can we obtain measured S-parameter data?
• Consider how best to build an adequate SPICE
  model (AC) based on device simulation results
• With a working SPICE model, estimate important
  high-frequency figures of merit and begin to
  design basic analog/RF circuits for system-level
  verification of power gain, noise, linearity