A Design Flow for MixedSignal IC Design in DIMOS01 Technology

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A Design Flow forMixed-Signal IC Design in
DIMOS01 Technology

• Arjan van Genderen

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Overview

• DIMOS01 Technology
• Design Flow for Cadence/Synopsys
• Mixed analog/digital design example
• Component/Cell Libraries
• Some Practical Remarks
• New Sea-Of-Gates Chip for OP
• Conclusions

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DIMOS01 Technology

• CMOS, nwell, 5V
• Minimum transistor dimensions
• width 2.4 ?m, length 1.6 ?m
• 2 metal layers
• Adopted from Philips (C3DM)
• Analog and digital applications

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Design Flow Supported Design Steps

• High-level digital modelling (Verilog)
• High-level analog modelling (Verilog-A)
• Schematic design
• Mixed-level simulation
• Layout design
• DRC

• Logic synthesis
• Placement and Routing (standard cells, arbitrary
  blocks)
• Extraction
• LVS
• Re-simulation
• GDS file generation

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The Design Example
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High-level Digital Modelling
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High-level Analog Modelling
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Schematic Design
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Schematic Including Pads
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Simulation

• Standard simulator
• spectre/spectreVerilog
• Input
• Electrical components
• Verilog
• Verilog-A
• Mixed-level simulation behavioral,
  logic, circuit

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Simulation Configuration
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Simulation Control
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Simulation Results
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Transistor Level Design
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Layout Design (1)
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Layout Design (2)
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DRC
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Logic Synthesis (1)

• Synopsys Design Compiler maps behavioral/RTL
  description to digital standard cells
• Input script
• search_path ., DESKIT_dimos01,
  synopsys_root /libraries/syn
• target_library dimos01Cells.db
• link_path dimos01Cells.db
• symbol_library class.sdb
• read -format verilog dimos01Tutorial/count3/funct
  ional/verilog.v
• compile
• report -area
• report -timing
• write -format verilog -output count3.v

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Logic Synthesis (2)
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Placement Standard Cells
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Routing Standard Cells
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Placement and Routing Chip
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P R Chip Adding Ring Fillers
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P R Chip Final Result
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Extraction (1)

• Extraction is run in macro-cell mode
• Cells are fully expanded (for pads and
  optionally - standard cells, only metal
  interconnect is expanded)
• Extraction of
• Components and their connections
• Interconnect capacitances
• Interconnect resistances

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Extraction (2)
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Extraction (3)
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LVS (1)
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LVS (2)
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Re-Simulation

• Simulation of the extracted netlist
• Check on layout connectivity
• Effect of interconnect parasitics
• 2 possibilities for simulation standard cells
• transistor level (layout instance expanded)
• logical level (layout instance not expanded)

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Chip Finishing

• Design is placed in SAW FRAME (die)

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GDS File Generation

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Component Library

• Nmos and pmos transistors (W, L)
• Resistors (r, nrOfBends)
• Vias

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Cell Library

• Digital standard cells
• Analog pad cells and digital pad cells
• OP-AMP and comparator

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Some Practical Remarks

• Running under HP-UX, SUN-OS and Linux
• Setting paths for Cadence
• source /opt/cad/cadence/5.0/sourceme
• Initializing design environment
• source /opt/cad/cadence/DesignKits/dimos01/sour
  ceme
• Tutorial
• http//warga.et.tudelft.nl/cadmgr/dimos01Tu
  torial
• Help-desk Arjan van Genderen, room 17.070, phone
  81796

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New OP Chip

• 7.5mm x 7.5mm
• 92,000 MOS transistors (Sea-of-Gates style) for
  digital cells
• Analog cells between pads (16 OpAmps, 16
  comparators, resistors, capacitors)
• Suited for layout design with OCEAN / Nelsis

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Conclusions

• A design kit for CMOS ICs in DIMOS01
• Analog
• Digital
• Mixed Analog/Digital
• Full-Custom
• Standard Cell
• Running on HP-UX, Sun Solaris, Linux