Congestiondriven Codesign of Power and Signal Networks

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Congestion-driven Co-design of Power and Signal
Networks

• Haihua Su, IBM Corp.
• Jiang Hu, IBM Corp.
• Sachin S. Sapatnekar, Univ. of Minnesota
• Sani R. Nassif , IBM Corp.

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Outline

• Motivations and challenges
• Overview of the flow
• Congestion-driven global routing and power grid
  design
• Overall scheme (PSiCo)
• Experimental results

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Motivations

• Interconnect is increasingly critical to
  performance
• Global power and signal wires compete for routing
  resources (routing area and buffers)
• Optimal use of routing resources
• Design power grid with non-uniform pitches
• Avoid signal nets routing into hot spots of a
  chip

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Challenges

• Power grid
• To provide reliable Vdd and GND signals
  throughout the chip
• Voltage fluctuation can lead to spurious
  transitions, delay variations and timing
  unpredictability

Vdd
vin
vout
GND
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Challenges (Contd)

• Global signal routing
• Shortest-path Detour at highly-congested regions
• Nets correlated with each other while
  contributing to the congestion
• Becomes more complicated with the consideration
  of power grids

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Outline

• Motivations and challenges
• Overview of the flow
• Congestion-driven global routing and power grid
  design
• Overall scheme (PSiCo)
• Experimental results

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Congestion-driven Design Flow
Power Grid
Macros or Cells
Signal Netlists
Global Router
Power Wire Removal Power Grid Sizing
Congestion Map
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Overview of Our Scheme

• Initial power grid uniformly distributed
• Congestion-driven power grid-aware global
  routing and congestion map generation
• Power grid adjustment scheme
• Congestion map update and rip-up-and-reroute

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How is the improvement?

• Signal routing capacity along the tile boundary
  is increased
• Power grids around this region are sized after
  removal

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Outline

• Motivations and challenges
• Overview of the flow
• Congestion-driven global routing and power grid
  design
• Overall scheme (PSiCo)
• Experimental results

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Power Grid-aware Congestion Estimation
Signal wire
Power wire
Capacity
Num signal wires S(b) Overflow S(b)
T(b) Density S(b)/T(b)
W(b)
tiles
Congestion Map tiles boundaries with positive
overflow values
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Congestion-driven Global Routing

• Initial Steiner tree construction
• Iterative rip-up-and-reroute till Density ? 1
• Min-max tree built on the dual of the tile graph
• Edge weight(tile boundary capacity T(b) is power
  grid-aware)

- C. Chiang and M. Sarrafzadeh, Global Routing
Based on Steiner Min-max Tree, IEEE Transactions
on Computer-Aided Design, vol. 9, pp. 1318-1325,
Dec. 1990.
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Two-step Power Grid Design Scheme

• Power wire removal heuristic
• Congestion-driven
• Noise-aware
• Power grid sizing
• For performance compensation
• Constrained nonlinear programming

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Heuristic Power Wire Removal

• Definitions
• Critical wires power wires with Vmaxgt VDPth
• Non-critical wires power wires with Vmax? VDPth
• Criticality of a non-critical wire reciprocal of
  average distance to critical nodes with nonzero
  noise within its closest region

Criticality
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Removal Illustration
Critical wires 1, 2, 4 and 6
Removal order first 3 then 5
Non-Critical wires 3 and 5
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Removal Illustration (Contd)
Removal order first b then a
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Heuristic Removal Procedure

• Sort tile boundaries in decreasing order of their
  overflow values (The larger the overflow value
  is, the more congested the region is.)
• Sort all non-critical power wires in increasing
  order of their criticality values (The larger the
  criticality value is, the closer the power wire
  is to the hot spot.)
• In the order of the sorted tile boundaries,
  remove non-critical power wires in the order of
  their criticality
• Dynamically update overflow values during removal
• Assert an upper bound for the number of wires to
  be removed in one iteration before wire sizing
  optimization

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Power Network Modeling

• Power Grid resistive mesh
• Cells time-varying current sources
• Decaps lumped capacitors
• Package inductance ideal constant voltage
  source

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Power Grid Sizing Formulation

• Minimize
• Subject to Z (wj) lt ?
• And wmin ? wj ? wmax , j 1.. Nwire

V(t)
VDD
90VDD
Noise Z voltage drop integral
t
O
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Power Grid Sizing Procedure
Constraint function Z from transient simulation
of original circuit
Objective function A ? li wi
Construct adjoint circuit and add current sources
to failure nodes
SQP solver update wi
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Outline

• Motivations and challenges
• Overview of the flow
• Congestion-driven global routing and power grid
  design
• Overall scheme (PSiCo)
• Experimental results

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Overall Scheme (PSiCo)

• Generate the congestion map
• Transient simulation of the power grid circuit
• Sort tile boundaries and non-critical wires
• Heuristic power wire removal and grid sizing
• Update the congestion map, rip-up-and-reroute
  congested nets

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Outline

• Motivations and challenges
• Overview of the flow
• Congestion-driven global routing and power grid
  design
• Overall scheme (PSiCo)
• Experimental results

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Experimental Results

• Benchmark circuits
• 0.18?m technology, Vdd1.8V
• Global wires on layer M3 M4 (wmin0.8 ?m and
  wmax4 ?m)

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Test Circuits and Run Time of PsiCo
Pentium-IV 1.8GHz, 256M memory
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Congestion Improvement and Optimal Power Grid
Results
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Result of Circuit ac3
Voltage droop contour
Congestion map
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Optimal Power Grid of ac3 (M3 M4)
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Sized Grid
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Conclusion

• Created a novel scheme for the co-design of
  signal and power networks
• The overall flow is congestion-driven
• The co-design of signal and power wires is
  closely-coupled to each other
• Presented several power grid removal heuristics
  and a quadratic programming based power grid
  sizing approach

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Thank you!