Rapid Development of a Flexible Validated Processor Model

1
Rapid Development of a Flexible Validated
Processor Model

• David A. Penry
• Manish Vachharajani
• David I. August
• The Liberty Architecture Research Group
• Princeton University
• Dept. of Electrical and Computer Engineering
• University of Colorado, Boulder

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Architectural Exploration

• Want baseline simulator to be validated
• Want rapid model changes (flexibility)

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Why are flexible, validated simulators hard?

• Barriers to flexibility
• Concurrent hardware, but sequential simulators
• Lack of reuse
• Validation 3 kinds of errors Black Shen, 98
• Specification knowing what to model
• Abstraction deciding how much to model
• Modeling doing it right
• Liberty Simulation Environment addresses
  flexibility and modeling error through
  concurrent structural modeling

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The Itanium 2
Register Renaming uOp insertion
BranchResolution
EXP
REN
REG
EXE
DET
WRB
DCU
Structural Hazard Detection
Data Hazard Detection

• 11 weeks, 1 designer
• Systematic, incremental approach

5
Designing the model Front-end
EXP
REN
REG
EXE
DET
WRB
DCU
Investigation
Modeling
6
Designing the model EXP
REN
REG
EXE
DET
WRB
EXP
DCU
Investigation
Modeling
7
Designing the model REN
REG
EXE
DET
WRB
EXP
REN
DCU
Investigation
Modeling
8
Designing the model Rest of backend
EXP
REN
DCU
Investigation
Modeling
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Designing the model DCU
EXP
REN
DCU
Investigation
Modeling
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Initial model results
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Is this good enough?

• Evaluate effectiveness of instruction prefetching
  (186.crafty)

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Initial model component analysis
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Refinements Front end

• Added prefetch unit

I-BUF
ROT
EXP
REN
IPG
DCU
Investigation
Modeling
14
Refinements L1D

• Fix page size
• Add real hardware page table walk

I-BUF
ROT
EXP
REN
IPG
DCU
Investigation
Modeling
15
Refinements Load-use stalls

• Add detailed L2/L3 cache behavior

I-BUF
ROT
EXP
REN
IPG
DCU
Investigation
Modeling
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Refined model component analysis
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Comparison of component errors
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Refined model results
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Uses of the model within our group

• New pipeline organization with re-cycling of
  instructions (4 weeks)
• Rangan, et al. Decoupled Software Pipelining
  with the Synchronization Array. PACT 04. (2
  weeks)
• Reis, et al. Design and Evaluation of Hybrid
  Fault-Detection Systems. ISCA-32. (a few hours
  to modify, a couple days to learn LSE)

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Conclusions

• Liberty Simulation Environment is effective at
  reducing modeling errors and increasing
  flexibility
• To control abstraction and specification errors
• Use disciplined refinement investigate, decide,
  model
• Quantitatively verify documents
• Quantitatively verify abstractions
• Single metrics are not enough to validate models

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Backup slides
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Simulator Construction Systems

• Reuse simulator infrastructure

• But still must be able to reuse descriptions
• Structural composition
• Medium-grained components
• Standard communication contracts
• High parameterizability
• Separation of concerns

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This study Itanium 2

• HW complexity ? model complexity
• 11 weeks, 1 designer

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Liberty Simulation Environment

• Simulator construction system for high reuse
• Two-tiered specifications
• Leaf module templates in C
• Netlisting language for instantiation and
  customization
• Three-signal standard communications contract
  with overrides (control functions)
• Code is generated

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Shapes
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Designing the model
EXP
REN
REG
EXE
DET
WRB
DCU
Investigation
Modeling