Customisable FPGA Platform for Accelerating Floating Point Computations

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Customisable FPGA Platform for Accelerating
Floating PointComputations

• Transfer examination
• Chun Hok Ho
• cho_at_doc.ic.ac.uk

2 February 2007
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Motivations

• Floating Point Applications are important
• Molecular dynamics
• Physics problems
• Differential equations
• Linear systems
• Graphics transformation
• Financial engineering

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Motivations

• Current computing platform for floating point
  application
• Processor-based platform
• General purpose
• Restricted to von Neumann architecture
• Not dedicate to floating point computations
• FPGA-based platform
• An approach to accelerate computations
• Speedup 10x 1000x against general purpose
  processor
• Not dedicate to floating point computations

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Objectives

• Methodology for inventing new FPGA architecture
• Customisable
• Design exploration
• Novel customisable FPGA architecture
• Efficient floating point computation
• Similar programmability as the current FPGA
• Associated tools for supporting the architecture,
  model and methodology

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Related work (architecture)

• Fine-grained FPGA (Virtex, Stratix)
• Embedded blocks (multiplier, DSP)
• Fixed point computations
• Coarse-grained FPGA
• ADRES
• RaPiD
• Datapath FPGA

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Related work (modelling)

• Versatile Place and Route (VPR)
• place and route on virtual FPGA
• flexible architectural parameters
• XC4000X device
• some version includes carry chain, embedded
  multiplier, block memory

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Related work (applications)

• Financial engineering interest rate derivatives
  
• Image processing K-means clustering
• Physics simulation N-body problem
• Signal processing Fast Hartley Transform (FHT)
• Video processing noise reducer

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Methodology

• How to model an FPGA architecture?
• What fine-grained architecture?
• What coarse-grained architecture?
• How to evaluate an FPGA architecture?

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Methodology

• Modelling
• Commercial place and route tool
• Synthesisable FPGA fabric model
• Exploration
• Fine-grained / coarse-grained
• Embedding various floating point cores
• Evaluation
• Benchmark circuits
• Compare to existing commercial device

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Benchmark circuits

• Floating point unit
• single/double precision, fully pipelined,
  subnormal number
• Adder and multiplier
• implement on ASIC and FPGA
• Floating Point benchmark circuits
• butterfly (bfly), digital sine-cosine generator
  (dscg), FIR (fir4), ordinary differential
  equation solver (ode), 3 x 3 matrix multiplier
  (mm3), Monte Carlo simulation (bgm)

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Modelling

• Virtual embedded block design flow
• Current vendors place and route tools to explore
  the system performance of embedding various ASIC
  design, e.g. (block multiplier / FPU)
• Synthesisable Datapath FPGA design flow
• Fabric generator to develop both generalised and
  domain specific customisable datapath oriented
  FPGAs

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Virtual embedded blocks (VEB)

• Using logic cells to emulate embedded elements in
  FPGA
• Area ? area of logic cells
• Delay ? combinatorial delays of logic cells
• Position ? placement constraints
• Integrate into most of the development tools
  (commercial or academia)
• Requires timing analysis tool and floorplanner
• Retiming

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Virtual embedded blocks (VEB)

• Rapid exploration of embedded elements on
  existing FPGA
• Simple interface, complicated model
• Compare commercial FPGA directly
• Allow high quality synthesis and optimisation

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VEB design flows
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Synthesisable fabric

• Fabric described in RTL hardware description
  language
• Synthesisable standard ASIC tools (Synopsys
  Designer Compiler)
• Parameterised fabric
• Rapid evaluation

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Synthesisable fabric

• Product-term fine-grained synthesisable core

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Hybrid FPGA

• VEB model
• Arbitrary embedded elements
• Vendor specific fine-grained fabric
• Dedicated to fine-grained architecture
• Synthesisable model
• Parameterised coarse-grained fabric
• Dedicated to coarse-grained architecture
• Combined both?

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Hybrid FPGA

• Most digital circuits
• Control logic ? irregular, bit-based logic
• Datapath ? regular, bus-based logic
• Hybrid FPGA
• Fine-grained resources ? control logic
• Coarse-grained resources ? datapath

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Hybrid FPGA architecture
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Coarse-grained fabric
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Example floorplan
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Future plan

• 6 month internship at Xilinx Inc., starting next
  week
• Aug 2007 Nov 2007 develop high level synthesis
  algorithm
• Dec 2007 Mar 2008 implement more complex
  floating point applications
• Apr 2008 Jun 2008 develop automatic hybrid
  FPGA architecture generation algorithm
• Jul 2008 Nov 2008 thesis writeup

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Conclusions

• Research direction
• Floating Point FPGA
• Research methodology
• Modelling
• Architecture
• Future
• Automatic FPGA generation