Interconnect%20Complexity-Aware%20FPGA%20Placement%20Using%20Rent

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Interconnect Complexity-Aware FPGA Placement
Using Rents Rule

• G. Parthasarathy
• Malgorzata Marek-Sadowska
• Arindam Mukherjee
• Amit Singh
• University of California, Santa Barbara

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Outline

• Motivation
• Rents Parameter
• Analysis
• New Placement Algorithm
• Results
• Conclusions
• Future Work

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Motivation

• 80-90 of die area interconnects
• increased programmability
• routing resource utilization (RRU) is low
• 100 logic utilization
• unused LUTs -gt better RRU
• maybe at the cost of increased area?
• Maybe not!
• interconnect complexity guided placement - Rents
  parameter

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Rents Parameter

• Common measure for Interconnect Complexity
• Nio K NgP
• Nio Number of IO pins/terminals external to the
  logic partition
• K - Average number of interconnections per LUT
• Ng Number of LUTs in a logic partition
• p Rents parameter after E.F.Rent
• E.F.Rent,1960
• Landman, Russo, 1971

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Local Rents parameter Pld

• Complexity Varies across design.
• Solution Use local interconnect complexity
  measure based in interconnect length
  distributions. (Van Marck et al.,95)
• Reduces to Landmans Rents exponent for uniform
  design at the top level

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Rents Parameter

• Van Marck, Stroobandt, Campenhout, 1995
• p D(log Ni) / D(log Li)
• p Rents parameter
• Li - length of a net
• Ni - number of nets of length Li

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Rents Parameter
logNi
logLi
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Analysis

• Consists of LUTs, connection boxes and
  switch-boxes
• Regular 2-D mesh array of unit tiles

FPGA Architecture
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FPGA Fabric Min-Size-Up

• Definitions
• Pa Rents parameter for Architecture
• Pd Rents parameter for Design
• Case 1 Pd lt Pa
• Design routable. Try to get best placement.
• Case 2 Pd gt Pa
• Design Un-routable. Need more resources.
• Solution Increase FPGA fabric size by scaling
  factor C

Pa


Pd
)
K(C.N
K N
Nio
g
g
-
Pa
Pd

N
C
Pd
g
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New Placement Algorithm

• Simulated Annealing - VPR
• scale-up fabric by C
• modify VPRs existing Cost Function
• pld - pla used as scaling factor for
  bounding-box based cost function
• uniform distribution of interconnect complexity

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Place-and-Route CAD Flow

• Generate Benchmarks
• Known Pd
• Uniform Distribution
• Map to Net-list
• Place-and-route
• VPR
• MVPR
• Compare

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Results - Benchmarks
gnl generated ckts
p1d p2d p3d p4d p5d p6d
p6d
p5d
p4d
p1d
p2d
p3d
random ckts - ISCAS benchmarks
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Rents Parameter for Architecture1
Results

• Segmentation 1, channel width 7, Pa 0.62

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Rents parameter for Architecture2

• Segmentation 2, channel width 7, Pa 0.64

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Routing Utilization for seg 1

• MVPR produces better routing utilization
• 15-25 better

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Routing Utilization for seg 12

• MVPR produces better routing utilization
• 10-15 better

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Routing Utilization for seg 2

• MVPR produces only minimally better routing
  utilization
• 1-5 better

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Routing Overhead Results (MVPR vs VPR) seg 1

• results follow trend for changes in architecture

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CLB Area Utilization (MVPR v/s VPR) seg 1

• logic area utilization falls with increasing Pd

• results follow trend for changes in architecture

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• MVPR over VPR for gnl generated ckts
• 25 higher RRU
• 10-15 lower Area

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Minimum Tracks Required on ISCAS Ckts
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• MVPR over VPR for ISCAS ckts
• same track utilization
• 5 lower average wire length
• 2-5 higher RRU
• 10-15 higher Area

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Conclusions

• Pluses
• New Cost Function
• Minimum size fabric derived for Pd gt Pa
• Min-Area lt-gt Max-RRU
• Minuses
• Errors in the estimation of Pd and Pa
• second-order effects
• Non-uniform interconnect complexities

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Future Work

• Modifying MVPR
• non-uniform interconnect complexity
• timing/power-dissipation and complexity-aware
  FPGA placement
• correlating track segmentation with accurate
  estimation of Rents parameter