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Digital Design Combinational Logic Principles

Creditss adapted from J.F. Wakerly,

Digital Design, 4/e, Prentice Hall, 2006 C.H.

Roth, Fundamentals of Logic Design, 5/e, Thomson,

2004 A.B. Marcovitz, Intro. to Logic and Computer

Design, McGraw Hill, 2008 R.H. Katz, G.

Borriello, Contemporary Logic Design, 2/e,

Prentice-Hall, 2005

Combinational Logic

- Logic systems are classified into two types
- Combinational
- Sequential
- A combinational logic system is one whose current

outputs depend only on its current inputs - Combinational systems are memory-less. They do

contain feedback loops. - A feedback loop is a signal path that allows the

output signal of a system to propagate back to

the input of the system.

x1

y1

xn

ym

Analysis and Design of combinational logic systems

- Goal analysis and design of logic functions

whose current outputs depends only on their

current inputs - Represent each of the inputs and outputs as

binary patterns - Formalize the function specification of the

system in the form of a table or an algebraic

expression

Switching Algebra

- Switching algebra is binary
- that is all variables and constants take on one

of two values 0,1 - Switching algebra is based on three elementary

operations - NOT, AND, OR

NOT, AND, OR

NOT, AND, OR as switches

Switching Algebra Axioms

- Axioms ( postulates) of a mathematical system

minimal set of basic definitions from which all

other information can be derived

Principle of Duality

- Because of the duality of axioms any theorem in

switching algebra remains true as far as 0 and 1

are swapped and ? and are swapped.

Useful Properties of Switching Algebra

Operations with 0 and 1 1. X 0 X 1D. X 1

X 2. X 1 1 2D. X 0 0 Idempotent

Theorem 3. X X X 3D. X X

X Involution Theorem 4. (X' )' X Theorem

of Complementarity 5. X X' 1 5D. X X'

0

Useful Properties of Switching Algebra

Commutative law 6. X Y Y X 6D. X Y

Y X Associative law 7. (X Y) Z X (Y

Z) 7D. (X Y)Z X(Y Z) X Y Z

X Y Z Distributive law 8. X(Y

Z) XY XZ 8D. X YZ (X Y)(X Z)

Simplification theorems 9. XY XY'

X 9D. (X Y)(X Y' ) X 10. X XY X

10D. X(X Y) X 11. (X Y' )Y XY

11D. XY' Y X Y

Useful Properties of Switching Algebra

DeMorgan's laws 12. (X Y Z ...)'

X'Y'Z'... 12D. (XYZ...)' X' Y' Z' ...

Shannons Expansion Theorem 13. F(X,Y,Z, ...)

X F(1,Y,Z, ...) X' F(0,Y,Z, ...) 13D.

F(X,Y,Z, ...) X F(0,Y,Z, ...) X'

F(1,Y,Z, ...) Theorem for multiplying out and

factoring 14. (X Y)(X' Z) XZ X'Y

14D. XY X'Z (XZ)(X'Y) Consensus theorem

(muxing) 15. XY YZ X'Z X Y X'Z 15D.

(XY)(YZ)(X'Z) (XY)(X'Z)

Representations of Logic Functions

- Truth TablesTable that shows the output value

for each combination of the inputs. The truth

table for an n-variable (n-inputs) logic function

has 2n rows. - Algebraic expressions
- Karnaugh Maps

Common Terminology

- LiteralThe appearance of a variable or its

complement - Product Term
- One or more literals connected by AND operators
- Sum Term
- One or more literals connected by OR operators

Common Terminology (contd)

- Sum of Products (SOP)One or more product terms

connected by OR operator - Product of Sums (POS)One or more sum terms

connected by AND operator - Standard (Normal) Product Term also called

mintermA product term that includes each

variable of the problem either uncomplemented or

complemented

Common Terminology (contd)

- Canonical Sum (of products)Is a sum of minterms
- Standard ( Normal) Sum Term also called

maxtermA sum term that include each variable of

the problem, either uncomplemented or

complemented - Canonical Product (of sums)Is a product of

maxterms

Truth tables, minterms, and maxterms

- There is a close correspondence between the truth

table and minterms and maxterms - A minterm is a product term that is 1 in exactly

one row of the truth table - Similarly (by duality) a maxterm is a sum term

that is 0 in exactly one row of the truth table - An n-variable minterm can be represented by an

n-bit integer. Thus, we we can use mi to denote

the minterm corresponding row i of the truth

table. - For maxterm i (Mi), if the bit in the binary

representation of i is 1, the corresponding

variable is complemented

Truth tables, minterms, and maxterms

EXAMPLE

EXAMPLE

EXAMPLE

EXAMPLE Lessons Learned

- What is the best way (minimum) to express a logic

function ? - When can I stop with the algebraic manipulations ?

Logic functions representations

- So far, we have seen 3 ways for representing a

logic function - Truth Table
- Canonical SOP
- as algebraic sum of minterms or
- as list of minterms using the S notation
- Canonical POS
- as algebraic product of maxterms or
- as list of maxterms using the P notation
- and soon we will see one more called K-maps

But, the issue is still there how can we

minimize logic functions ?

- The minimum logic expression for a function is

the one with the fewest number of terms. If there

are more than one expression with the same number

of terms, the minimum is the one fewest number of

literals. - Since ultimately the goal of digital design is to

come out with a circuit that implements the given

logic function, lets see what does minimization

mean from a circuit perspective

Minimization

- A function in its canonical form (both SOP and

POS) produce a 2-level circuit implementation

Minimization (contd)

Minimization (contd)

Minimization (contd)

- Minimization methods reduce the cost of a 2-level

circuit in two ways - Minimizing the number of first-level gates
- As a side effect the number of inputs on the

second level gates results also minimized - Minimizing the number of inputs on each first

level gate

Minimization (contd)

- Key tool to simplification is the uniting

theorem A (B B) A - Essence of simplification of two-level logic
- find two element subsets of the ON-set where only

one variable changes its value this single

varying variable can be eliminated and a single

product term used to represent both elements

F ABAB (AA)B B

A B F 0 0 1 0 1 0 1 0 1 1 1 0

Multilevel Logic (3-level or more)

Implementation of Boolean functions with AND, OR

and NOT gates

NAND gate

NAND circuit

X

Y

x

y

z

3V

3 volts

3 volts

Z

3 volts

0V

0 volts

NAND-NAND logic

De-Morgan Graphically

NOR gate

NOR circuit

X

Y

x

y

z

3v

3 volts

0 volts

Z

0 volts

0v

0 volts

NOR-NOR logic

De-Morgan Graphically

Summarizing

- OR is the same as NAND with complemented inputs
- AND is the same as NOR with complemented inputs
- NAND is the same as OR with complemented inputs
- NOR is the same as AND with complemented inputs

XOR and XNOR gates

- XOR
- XNOR

X

Z

X?Y X?Y X?Y

Y

X?Y expresses "inequality", "difference" (X ? Y)

X

X?Y X?Y X?Y

Z

Y

X xnor Y expresses "equality", "coincidence" (X ?

Y)

Exclusive OR Properties

- X?0 X
- X?1 X
- X?X X
- X?X 0
- X?Y Y?X (commutative law)
- (X?Y)?Z X?(Y?Z) X?Y?Z (associative law)
- X(Y?Z) XY?XZ (distributive law)
- (X?Y) X?Y X?Y XY XY

Choosing different realizations of a function

two-level realization(we dont count NOT gates)

multi-level realization(gates with fewer inputs)

XOR gate (easier to draw but costlier to build)

Which realization is best?

- Reduce number of inputs
- literal input variable (complemented or not)
- can approximate cost of logic gate as 2

transistors per literal - why not count inverters?
- fewer literals means smaller gates
- smaller gates means less transistors
- fewer inputs implies faster gates
- gates are smaller and thus also faster
- fan-ins ( of gate inputs) are limited in some

technologies - Reduce number of gates
- fewer gates (and the packages they come in) means

smaller circuits - directly influences manufacturing costs

Which realization is best? (contd)

- Reduce number of levels of gates
- fewer level of gates implies reduced signal

propagation delays - How do we explore tradeoffs between increased

circuit delay and size? - automated tools to generate different solutions
- logic minimization reduce number of gates and

complexity - logic optimization reduction while trading off

against delay

K-Maps

- A K-map is a graphical representation of a logic

functions truth table (it helps visualize

adjacencies and as result it makes easier to

apply the uniting theorem ) - The map for an n-input function is an array with

2n cells, one cell for each possible input

combination (minterm) - K-maps are a flat representation of Boolean

cubes

A B C F 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1

0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

(A'A)BC

AB(C'C)

111

F BCABAC

B

C

101

A(BB')C

000

A

K-maps (conts)

- K-maps adjacencies wrap around edges
- Wrap from first to last column
- Wrap top row to bottom row
- Numbering scheme is based on Graycode (only a

single bit changes in code for adjacent map cells - K-maps are hard to draw and visualize for more

than 4 dimensions, and virtually impossible for

more than 6 dimensions

K-maps (contd)

K-map examples

K-maps examples (contd)

K-maps examples (contd)

Applying the uniting Theorem

Function with Two Minimal Forms

K-maps examples (contd)

K-map examples (contd)

K-map examples (contd)

- f(A,B,C)
- f(A,B,C) ?m(0,4,5,7)

What about the complement of functions ?

We can obtain the complement of functions by

covering 0s with subcubes

K-map examples (contd)

Function F and its complement G

K-maps examples (contd)

F(A,B,C,D) ?m(0,2,3,5,6,7,8,10,11,14,15)

A

1 0 0 1

0 1 0 0

D

1 1 1 1

1 1 1 1

C

B

K-maps examples (contd)

K-map 5-variables example

Incompletely specified functions (dont cares)

- Sometime, not all input combinations are

specified

- f(A,B,C,D) Sm(1,3,5,7,9) d(6,12,13)
- f

without dont cares

Karnaugh maps dont cares (contd)

- f(A,B,C,D) ??m(1,3,5,7,9) d(6,12,13)
- f A'D B'C'D without don't cares
- f with don't cares

don't cares can be treated as 1s or 0sdepending

on which is more advantageous

Map Entered Variables

Map Entered Variables (contd)

Map with entered variables and its equivalent

expanded version

Map Entered Variables (contd)

More Terminology

- Implicant of a function Fa single 1 ( minterm)

or any group of 1s which can be combined

together in a K-map (i.e., 1s that are adjacent

and which are grouped in a number that is always

a power of 2). represents a product term which

is called an implicant of a function F. An

implicant represents a product term that can be

used in a SOP expression for that function, that

is, the function is 1 whenever the implicant is 1

(and maybe other times, as well ) - Prime Implicantis an implicant that cannot be

combined with another one to eliminate a literal.

In other word each prime implicant corresponds to

a product term in one of the minimum SOP

expression for the function. A prime implicant is

an implicant that is not fully contained in any

other implicant. - Essential prime implicantis a prime implicant

that includes at least one 1 that is not included

in any other prime implicant. In other words if a

particular element of the on-set is covered by

only one prime implicant, than that implicant is

called an essential prime implicant.

Implicants

The implicants of F are

Prime Implicants

Essential Prime Implicants

Essential Prime Implicants (contd)

More examples to illustrate terms

minimum cover AC BC' A'B'D

minimum cover 4 essential implicants

Activity

- List all prime implicants for the following

K-map - Which are essential prime implicants?
- What is the minimum cover?

BD

CD

ACD

BD

CD

ACD

Algorithm for determining a minimum SOP using a

K-map

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