IEEE 2015 VLSI AN ACCURACY-ADJUSTMENT FIXED-WIDTH BOOTH MULTIPLIER BASED ON MULTILEVEL.pptx - PowerPoint PPT Presentation

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IEEE 2015 VLSI AN ACCURACY-ADJUSTMENT FIXED-WIDTH BOOTH MULTIPLIER BASED ON MULTILEVEL.pptx

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Title: IEEE 2015 VLSI AN ACCURACY-ADJUSTMENT FIXED-WIDTH BOOTH MULTIPLIER BASED ON MULTILEVEL.pptx


1
AN ACCURACY-ADJUSTMENT FIXED-WIDTH BOOTH
MULTIPLIER BASED ON MULTILEVEL CONDITIONAL
PROBABILITY
2
ABSTRACT
  • In this paper, a reliable low-powermultiplier
    design is proposed by adopting algorithmic noise
    tolerant (ANT)architecture with the ?xed-width
    multiplier to build the reducedprecision replica
    redundancy block (RPR). The proposed
    ANTarchitecture can meet the demand of high
    precision, low powerconsumption, and area
    ef?ciency. We design the ?xed-width RPRwith error
    compensation circuit via analyzing of probability
    andstatistics.

3
  • Using the partial product terms of input
    correctionvector and minor input correction
    vector to lower the truncationerrors, the
    hardware complexity of error compensation
    circuitcan be simpli?ed. In a 12 12 bit ANT
    multiplier, circuitarea in our ?xed-width RPR can
    be lowered by 44.55 andpower consumption in our
    ANT design can be saved by 23 ascompared with
    the state-of-art ANT design.

4
EXISTING METHODS
  • 1. An aggressive low-power technique, referred to
    as voltageoverscaling (VOS), to lower supply
    voltage beyond critical supply voltage without
    sacri?cing the throughput. However, VOS leads to
    severe degradationin signal-to-noise ratio (SNR).
  • 2. RPR technique in the ANT design can operate
    fastly, but their hardware implementation is too
    complex.

5
PROPOSED METHOD
  • The ?xed-width RPR is proposed to replace the
    full-width RPR block. Using the ?xed-width RPR,
    the computation error canbe corrected with lower
    power consumption and lower areaoverhead. In
    order not to increasethe critical path delay, the
    compensation circuit is restricted and the RPR
    must not be located in the critical path. As a
    result, the ANT design with smaller circuit area,
    lowerpower consumption, and lower critical supply
    voltage is obtained.The ANT technique includes
    both main digitalsignal processor (MDSP) and
    error correction (EC) block.

6
(No Transcript)
7
ADVANTAGES
  • 1. Reduces the area
  • 2. Reduces the power
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